- 26 Jun, 2023 3 commits
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Stephen Boyd authored
Merge branches 'clk-imx', 'clk-microchip', 'clk-cleanup', 'clk-bindings', 'clk-ti' and 'clk-kasprintf' into clk-next - Handle allocation failures from kasprintf() and friends * clk-imx: clk: imx: clk-imx8mp: improve error handling in imx8mp_clocks_probe() clk: imx93: fix memory leak and missing unwind goto in imx93_clocks_probe clk: imx: clk-imx8mn: fix memory leak in imx8mn_clocks_probe dt-bindings: clock: imx8m: Add missing interrupt property clk: imx: clk-imxrt1050: fix memory leak in imxrt1050_clocks_probe clk: imx: composite-8m: Add imx8m_divider_determine_rate clk: imx: scu: use _safe list iterator to avoid a use after free clk: imx: drop imx_unregister_clocks clk: imx6ul: retain early UART clocks during kernel init clk: imx: imx6sx: Remove CLK_SET_RATE_PARENT from the LDB clocks * clk-microchip: dt-bindings: clocks: at91sam9x5-sckc: convert to yaml dt-bindings: clocks: atmel,at91rm9200-pmc: convert to yaml clk: microchip: Use of_property_read_bool() for boolean properties clk: microchip: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIRE * clk-cleanup: clk: fix typo in clk_hw_register_fixed_rate_parent_data() macro clk: Fix memory leak in devm_clk_notifier_register() clk: mvebu: Iterate over possible CPUs instead of DT CPU nodes clk: mvebu: Use of_get_cpu_hwid() to read CPU ID MAINTAINERS: Add Marvell mvebu clock drivers clk: mvebu: Use of_address_to_resource() clk: tegra: tegra124-emc: Fix potential memory leak clk: clocking-wizard: Fix Oops in clk_wzrd_register_divider() clk: bcm: rpi: Fix off by one in raspberrypi_discover_clocks() clk: sifive: Use devm_platform_ioremap_resource() * clk-bindings: dt-bindings: clock: drop unneeded quotes and use absolute /schemas path dt-bindings: rcc: stm32: Sync with u-boot copy for STM32MP13 SoC * clk-ti: clk: keystone: syscon-clk: Add support for audio refclk dt-bindings: clock: Add binding documentation for TI Audio REFCLK dt-bindings: clock: ehrpwm: Remove unneeded syscon compatible clk: keystone: syscon-clk: Allow the clock node to not be of type syscon * clk-kasprintf: clk: clocking-wizard: check return value of devm_kasprintf() clk: ti: clkctrl: check return value of kasprintf() clk: keystone: sci-clk: check return value of kasprintf() clk: si5341: free unused memory on probe failure clk: si5341: check return value of {devm_}kasprintf() clk: si5341: return error if one synth clock registration fails clk: cdce925: check return value of kasprintf() clk: vc5: check memory returned by kasprintf() -
Stephen Boyd authored
Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-samsung' and 'clk-amlogic' into clk-next - Make clk_ops::determine_rate mandatory for muxes * clk-renesas: clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic() clk: renesas: mstp: Convert to readl_poll_timeout_atomic() clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic() iopoll: Do not use timekeeping in read_poll_timeout_atomic() iopoll: Call cpu_relax() in busy loops clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write clk: renesas: r8a779a0: Add PWM clock * clk-determine-rate: (71 commits) clk: sprd: composite: Simplify determine_rate implementation ASoC: tlv320aic32x4: pll: Remove impossible condition in clk_aic32x4_pll_determine_rate() clk: Fix best_parent_rate after moving code into a separate function clk: Forbid to register a mux without determine_rate ASoC: tlv320aic32x4: div: Switch to determine_rate ASoC: tlv320aic32x4: pll: Switch to determine_rate clk: tegra: super: Switch to determine_rate clk: tegra: periph: Switch to determine_rate clk: stm32: composite: Switch to determine_rate clk: st: flexgen: Switch to determine_rate clk: sprd: composite: Switch to determine_rate clk: ingenic: tcu: Switch to determine_rate clk: ingenic: cgu: Switch to determine_rate clk: imx: scu: Switch to determine_rate clk: da8xx: clk48: Switch to determine_rate clk: si5351: clkout: Switch to determine_rate clk: si5351: msynth: Switch to determine_rate clk: si5351: pll: Switch to determine_rate clk: si5341: Switch to determine_rate clk: cdce706: clkout: Switch to determine_rate ... * clk-allwinner: clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux * clk-samsung: clk: samsung: add CONFIG_OF dependency clk: samsung: Re-add support for Exynos4212 CPU clock clk: samsung: Add Exynos4212 compatible to CLKOUT driver dt-bindings: clock: samsung,exynos: add Exynos4212 clock compatible * clk-amlogic: MAINTAINERS: repair pattern in ARM/Amlogic Meson SoC CLOCK FRAMEWORK clk: meson: pll: remove unneeded semicolon clk: meson: a1: Staticize rtc clk clk: meson: a1: add Amlogic A1 Peripherals clock controller driver clk: meson: a1: add Amlogic A1 PLL clock controller driver clk: meson: introduce new pll power-on sequence for A1 SoC family clk: meson: make pll rst bit as optional dt-bindings: clock: meson: add A1 Peripherals clock controller bindings dt-bindings: clock: meson: add A1 PLL clock controller bindings
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Stephen Boyd authored
- Migrate platform clk drivers to .remove_new() - Migrate i2c clk drivers to .probe() instead of .probe_new() - Remove CLK_SET_PARENT from all Mediatek MSDC core clocks - Add infra_ao reset support for Mediatek MT8188 SoCs - Align driver_data to i2c_device_id tables in some i2c clk drivers - Use device_get_match_data() in vc5 clk driver * clk-platform: clk: mediatek: Convert all remaining drivers to platform_driver's .remove_new() clk: mediatek: Make mtk_clk_pdev_remove() return void clk: mediatek: Make mtk_clk_simple_remove() return void * clk-i2c: clk: si521xx: Switch i2c driver back to use .probe() clk: Switch i2c drivers back to use .probe() * clk-mediatek: clk: mediatek: clk-mt8173-apmixedsys: Fix iomap not released issue clk: mediatek: clk-mt8173-apmixedsys: Fix return value for of_iomap() error clk: mediatek: clk-mtk: Grab iomem pointer for divider clocks clk: mediatek: fix of_iomap memory leak clk: mediatek: reset: add infra_ao reset support for MT8188 dt-bindings: reset: mt8188: add thermal reset control bit clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag clk: mediatek: Enable all MT8192 clocks by default * clk-i2cid: clk: rs9: Fix .driver_data content in i2c_device_id clk: vc7: Fix .driver_data content in i2c_device_id clk: vc5: Fix .driver_data content in i2c_device_id * clk-vc5: clk: vc7: Use device_get_match_data() instead of of_device_get_match_data() clk: vc5: Use device_get_match_data() instead of of_device_get_match_data()
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- 20 Jun, 2023 5 commits
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Claudiu Beznea authored
clk_hw_register_fixed_rate_parent_data() 3rd parameter is parent_data not parent_hw. Inner function (__clk_hw_register_fixed_rate()) is called with parent_data parameter as valid. To have this parameter taken into account update the name of the 3rd parameter of clk_hw_register_fixed_rate_parent_data() macro to parent_data. Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20230615101931.581060-1-claudiu.beznea@microchip.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Fei Shao authored
devm_clk_notifier_register() allocates a devres resource for clk notifier but didn't register that to the device, so the notifier didn't get unregistered on device detach and the allocated resource was leaked. Fix the issue by registering the resource through devres_add(). This issue was found with kmemleak on a Chromebook. Fixes: 6d30d50d ("clk: add devm variant of clk_notifier_register") Signed-off-by:
Fei Shao <fshao@chromium.org> Link: https://lore.kernel.org/r/20230619112253.v2.1.I13f060c10549ef181603e921291bdea95f83033c@changeidReviewed-by:
Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
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Rob Herring authored
Rework iterating over DT CPU nodes to iterate over possible CPUs instead. There's no need to walk the DT CPU nodes again. Possible CPUs is equal to the number of CPUs defined in the DT. Using the "reg" value for an array index is fragile as it assumes "reg" is 0-N which often is not the case. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230327-mvebu-clk-fixes-v2-3-8333729ee45d@kernel.orgSigned-off-by:
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Rob Herring authored
Use of_get_cpu_hwid() rather than the open coded reading of the CPU nodes "reg" property. The existing code is in fact wrong as the "reg" address cells size is 2 cells for arm64. The existing code happens to work because the DTS files are wrong as well. Signed-off-by:
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Rob Herring authored
drivers/clk/mvebu/ is missing a maintainers entry. Add it to the existing entry for the Marvell mvebu platforms. Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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- 17 Jun, 2023 8 commits
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Claudiu Beznea authored
devm_kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 2046338d ("ARM: mxs: Use soc bus infrastructure") Signed-off-by:
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Claudiu Beznea authored
kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 85204959 ("clk: ti: clkctrl: convert subclocks to use proper names also") Fixes: 6c309052 ("clk: ti: clkctrl: Fix hidden dependency to node name") Signed-off-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Claudiu Beznea authored
kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: b745c079 ("clk: keystone: Add sci-clk driver support") Depends-on: 96488c09 ("clk: keystone: sci-clk: cut down the clock name length") Signed-off-by:
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Claudiu Beznea authored
Pointers from synth_clock_names[] should be freed at the end of probe either on probe success or failure path. Fixes: b7bbf6ec ("clk: si5341: Allow different output VDD_SEL values") Fixes: 9b13ff43 ("clk: si5341: Add sysfs properties to allow checking/resetting device faults") Signed-off-by:
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Claudiu Beznea authored
{devm_}kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 3044a860 ("clk: Add Si5341/Si5340 driver") Signed-off-by: -
Claudiu Beznea authored
In case devm_clk_hw_register() fails for one of synth clocks the probe continues. Later on, when registering output clocks which have as parents all the synth clocks, in case there is registration failure for at least one synth clock the information passed to clk core for registering output clock is not right: init.num_parents is fixed but init.parents may contain an array with less parents. Fixes: 3044a860 ("clk: Add Si5341/Si5340 driver") Signed-off-by:
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Claudiu Beznea authored
kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 19fbbbbc ("Add TI CDCE925 I2C controlled clock synthesizer driver") Depends-on: e665f029 ("clk: Convert to using %pOFn instead of device_node.name") Signed-off-by:
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Claudiu Beznea authored
kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: f491276a ("clk: vc5: Allow Versaclock driver to support multiple instances") Signed-off-by:
Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by:
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- 16 Jun, 2023 8 commits
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AngeloGioacchino Del Regno authored
In case of error after of_ioremap() the resource must be released: call iounmap() where appropriate to fix that. Fixes: 41138fbf ("clk: mediatek: mt8173: Migrate to platform driver and common probe") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230615122051.546985-4-angelogioacchino.delregno@collabora.comReviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Signed-off-by:
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AngeloGioacchino Del Regno authored
The of_iomap() function returns NULL in case of error so usage of PTR_ERR() is wrong! Change that to return -ENOMEM in case of failure. Fixes: 41138fbf ("clk: mediatek: mt8173: Migrate to platform driver and common probe") Signed-off-by:
Markus Schneider-Pargmann <msp@baylibre.com> Signed-off-by:
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AngeloGioacchino Del Regno authored
In the rare case in which one of the clock drivers has divider clocks but not composite clocks, mtk_clk_simple_probe() would not io(re)map, hence passing a NULL pointer to mtk_clk_register_dividers(). To fix this issue, extend the `if` conditional to also check if any divider clocks are present. While at it, also make sure the iomem pointer is NULL if no composite/divider clocks are declared, as we are checking for that when iounmapping it in the error path. This hasn't been seen on any MediaTek clock driver as the current ones always declare composite clocks along with divider clocks, but this is still an important fix for a future potential KP. Fixes: 1fe074b1 ("clk: mediatek: Add divider clocks to mtk_clk_simple_{probe,remove}()") Signed-off-by:
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Jai Luthra authored
TI's AM62 SoC can optionally provide two audio reference clocks (AUDIO_REFCLKx) to external peripherals. By default this reference clock is looped-back inside the SoC to a mux that goes to McASP AHCLK, but can optionally be enabled as an output to peripherals outside the SoC by setting a bit through CTRL_MMR registers. This bit only controls the direction of the clock, while the parent is a muxed input from sci-clk [1] which may be a configurable PLL or a master clock from one of the McASP instances. Link: http://downloads.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html#clocks-for-board0-device [1] Signed-off-by:
Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20230515-refclk-v3-2-37c0b550f406@ti.comSigned-off-by:
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Jai Luthra authored
Add DT bindings for TI's audio reference clocks (REFCLK) present on AM62 SoC. Reviewed-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Andrew Davis authored
This node's register space is not accessed by any other node, which is the traditional use for the "syscon" hint. It looks to have been added here to make use of a Linux kernel helper syscon_node_to_regmap(). The Linux driver now uses a more appropriate helper that does not require the hint, so let's remove it from the binding. Signed-off-by:
Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230516184626.154892-2-afd@ti.comAcked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Andrew Davis authored
There is a helper device_node_to_regmap() we can use that does not force this clock DT node to be a "syscon" node. It should work the same in this case but allow us to remove the unneeded "syscon" compatible. Signed-off-by:
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https://github.com/BayLibre/clk-mesonStephen Boyd authored
Pull more Amlogic clk driver updates from Jerome Brunet: - Fix maintainers file pattern mistake - Remove unneeded semicolon * tag 'clk-meson-v6.5-2' of https://github.com/BayLibre/clk-meson: MAINTAINERS: repair pattern in ARM/Amlogic Meson SoC CLOCK FRAMEWORK clk: meson: pll: remove unneeded semicolon
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- 15 Jun, 2023 9 commits
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Krzysztof Kozlowski authored
Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint. Also absolute path starting with /schemas is preferred. Signed-off-by:
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Lukas Bulwahn authored
Commit e6c6ddb3 ("dt-bindings: clock: meson: add A1 PLL clock controller bindings") adds a file entry with pattern "include/dt-bindings/clock/a1*" to the ARM/Amlogic Meson SoC CLOCK FRAMEWORK section. However, all header files added in the patch series to add Amlogic A1 clock controller drivers carry the prefix "amlogic,a1", and there are not header files matching "a1*". Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a broken reference. Adjust the pattern of this file entry to match the headers actually added. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20230614084212.1359-1-lukas.bulwahn@gmail.com Fixes: e6c6ddb3 ("dt-bindings: clock: meson: add A1 PLL clock controller bindings") Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com>
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Jiapeng Chong authored
No functional modification involved. ./drivers/clk/meson/clk-pll.c:373:2-3: Unneeded semicolon. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Reviewed-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230614084808.98819-1-jiapeng.chong@linux.alibaba.com Fixes: b6ec400a ("clk: meson: introduce new pll power-on sequence for A1 SoC family") Signed-off-by:
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Rob Herring authored
Replace of_get_property() and of_translate_address() calls with a single call to of_address_to_resource(). Signed-off-by:
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Yuan Can authored
The tegra and tegra needs to be freed in the error handling path, otherwise it will be leaked. Fixes: 2db04f16 ("clk: tegra: Add EMC clock driver") Signed-off-by:
Yuan Can <yuancan@huawei.com> Link: https://lore.kernel.org/r/20221209094124.71043-1-yuancan@huawei.comAcked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Patrick Delaunay authored
Minor cosmetic change, aligned with files in U-Boot: - change obsolete SPDX id : GPL-2.0+ and use the same license GPL-2.0-only for the 2 files - use correct mail address gabriel.fernandez@foss.st.com - remove extra space Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20230510184305.v2.1.I417093ddcea282be479f10a37147d1935a9050b7@changeidAcked-by:
Gabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by:
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Dan Carpenter authored
Smatch detected this potential error pointer dereference clk_wzrd_register_divider(). If devm_clk_hw_register() fails then it sets "hw" to an error pointer and then dereferences it on the next line. Return the error directly instead. Fixes: 5a853722 ("staging: clocking-wizard: Add support for dynamic reconfiguration") Signed-off-by:
Michal Simek <michal.simek@amd.com> Signed-off-by:
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Dan Carpenter authored
Smatch detected an off by one in this code: drivers/clk/bcm/clk-raspberrypi.c:374 raspberrypi_discover_clocks() error: buffer overflow 'data->hws' 16 <= 16 The data->hws[] array has RPI_FIRMWARE_NUM_CLK_ID elements so the > comparison needs to changed to >=. Fixes: 12c90f3f ("clk: bcm: rpi: Add variant structure") Signed-off-by:Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Yang Li authored
Convert platform_get_resource(),devm_ioremap_resource() to a single call to devm_platform_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20230428070005.41192-1-yang.lee@linux.alibaba.comSigned-off-by:
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- 14 Jun, 2023 3 commits
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Stephen Boyd authored
Merge tag 'clk-microchip-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip Pull Microchip clk driver updates from Claudiu Beznea: Polarfire: - new Kconfig symbol name (SOC_MICROCHIP_POLARFIRE) for Microchip FPGA clock drivers PIC32: - use of_property_read_bool() to read "microchip,pic32mzda-sosc" boolean DT property in clk-pic32mzda AT91: - convert clock dt-bindings to YAML * tag 'clk-microchip-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: dt-bindings: clocks: at91sam9x5-sckc: convert to yaml dt-bindings: clocks: atmel,at91rm9200-pmc: convert to yaml clk: microchip: Use of_property_read_bool() for boolean properties clk: microchip: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIRE
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Stephen Boyd authored
Merge tag 'clk-imx-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx Pull i.MX clk driver updates from Abel Vesa: - Remove CLK_SET_RATE_PARENT flag from LDB clocks on i.MX6SX - Keep UART clocks enabled during kernel boot if earlycon is set - Drop the imx_unregister_clocks as there are no users for it - Switch to _safe iterator on imx_clk_scu_unregister to avoid use after free - Add determine_rate op to the imx8m composite clock - Use device managed API for iomap and kzalloc for i.MXRT1050, i.MX8MN, i.MX8MP and i.MX93 clock controller drivers - Add missing interrupt DT property for the i.MX8M clock controller * tag 'clk-imx-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx: clk-imx8mp: improve error handling in imx8mp_clocks_probe() clk: imx93: fix memory leak and missing unwind goto in imx93_clocks_probe clk: imx: clk-imx8mn: fix memory leak in imx8mn_clocks_probe dt-bindings: clock: imx8m: Add missing interrupt property clk: imx: clk-imxrt1050: fix memory leak in imxrt1050_clocks_probe clk: imx: composite-8m: Add imx8m_divider_determine_rate clk: imx: scu: use _safe list iterator to avoid a use after free clk: imx: drop imx_unregister_clocks clk: imx6ul: retain early UART clocks during kernel init clk: imx: imx6sx: Remove CLK_SET_RATE_PARENT from the LDB clocks
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Stephen Boyd authored
The sprd_div_helper_round_rate() function calls divider_round_rate() which calls divider_round_rate_parent() which calls divider_determine_rate(). This call chain converts back and forth from the rate request structure to make a determine_rate clk_op fit with a round_rate clk_op. Simplify the code here by directly calling divider_determine_rate() instead. This fixes a smatch warning where an unsigned long is compared to less than zero, which is impossible. This makes sprd_div_helper_round_rate() unnecessary as well so simply remove it and fold it into the only caller left. Reported-by:
Harshit Mogalapalli <harshit.m.mogalapalli@oracle.com> Closes: https://lore.kernel.org/r/45fdc54e-7ab6-edd6-d55a-473485608473@oracle.com Cc: Maxime Ripard <maxime@cerno.tech> Fixes: 302d2f83 ("clk: sprd: composite: Switch to determine_rate") Signed-off-by:
Maxime Ripard <mripard@kernel.org>
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- 13 Jun, 2023 4 commits
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Stephen Boyd authored
Smatch warns: sound/soc/codecs/tlv320aic32x4-clk.c:219 clk_aic32x4_pll_determine_rate() warn: unsigned 'rate' is never less than zero. Cc: Maxime Ripard <maxime@cerno.tech> Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202306101217.08CRVGcK-lkp@intel.com/ Fixes: 25d43ec3 ("ASoC: tlv320aic32x4: pll: Switch to determine_rate") Signed-off-by:
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Marek Szyprowski authored
best_parent_rate entry is still being used in the code and needs to be always updated regardless of the CLK_SET_RATE_NO_REPARENT flag. Fixes: 1b4e99fd ("clk: Move no reparent case into a separate function") Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20230613131631.270192-1-m.szyprowski@samsung.comAcked-by:
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Bosi Zhang authored
Smatch reports: drivers/clk/mediatek/clk-mtk.c:583 mtk_clk_simple_probe() warn: 'base' from of_iomap() not released on lines: 496. This problem was also found in linux-next. In mtk_clk_simple_probe(), base is not released when handling errors if clk_data is not existed, which may cause a leak. So free_base should be added here to release base. Fixes: c58cd0e4 ("clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers") Signed-off-by:Bosi Zhang <u201911157@hust.edu.cn> Reviewed-by:
Dongliang Mu <dzm91@hust.edu.cn> Link: https://lore.kernel.org/r/20230422084331.47198-1-u201911157@hust.edu.cnSigned-off-by:
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Runyang Chen authored
The infra_ao reset is needed for MT8188. - Add mtk_clk_rst_desc for MT8188. - Add register reset controller function for MT8188 infra_ao. - Add infra_ao_idx_map for MT8188. Signed-off-by:
Runyang Chen <runyang.chen@mediatek.com> Link: https://lore.kernel.org/r/20230525075011.7032-3-runyang.chen@mediatek.comReviewed-by:
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