1. 15 Nov, 2019 34 commits
  2. 14 Nov, 2019 6 commits
    • David S. Miller's avatar
      Merge branch 'Rework-mt762x-GDM-setup-flow' · 839554b7
      David S. Miller authored
      MarkLee says:
      
      ====================
      Rework mt762x GDM setup flow
      
      The mt762x GDM block is mainly used to setup the HW internal
      rx path from GMAC to RX DMA engine(PDMA) and the packet
      switching engine(PSE) is responsed to do the data forward
      following the GDM configuration.
      
      This patch set have three goals :
      
      1. Integrate GDM/PSE setup operations into single function "mtk_gdm_config"
      
      2. Refine the timing of GDM/PSE setup, move it from mtk_hw_init
         to mtk_open
      
      3. Enable GDM GDMA_DROP_ALL mode to drop all packet during the
         stop operation
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      839554b7
    • MarkLee's avatar
      net: ethernet: mediatek: Enable GDM GDMA_DROP_ALL mode · 8d66a818
      MarkLee authored
      Enable GDM GDMA_DROP_ALL mode to drop all packet during the
      stop operation. This is recommended by the mt762x HW design
      to drop all packet from GMAC before stopping PDMA.
      Signed-off-by: default avatarMarkLee <Mark-MC.Lee@mediatek.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8d66a818
    • MarkLee's avatar
      net: ethernet: mediatek: Refine the timing of GDM/PSE setup · 5ac9eda0
      MarkLee authored
      Refine the timing of GDM/PSE setup, move it from mtk_hw_init
      to mtk_open. This is recommended by the mt762x HW design to
      do GDM/PSE setup only after PDMA has been started.
      
      We exclude mt7628 in mtk_gdm_config function since it is a old IP
      and there is no GDM/PSE block on it.
      Signed-off-by: default avatarMarkLee <Mark-MC.Lee@mediatek.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5ac9eda0
    • MarkLee's avatar
      net: ethernet: mediatek: Integrate GDM/PSE setup operations · 8d3f4a95
      MarkLee authored
      Integrate GDM/PSE setup operations into single function "mtk_gdm_config"
      Signed-off-by: default avatarMarkLee <Mark-MC.Lee@mediatek.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8d3f4a95
    • Vladimir Oltean's avatar
      net: dsa: sja1105: Simplify reset handling · abfb228a
      Vladimir Oltean authored
      We don't really need 10k species of reset. Remove everything except cold
      reset which is what is actually used. Too bad the hardware designers
      couldn't agree to use the same bit field for rev 1 and rev 2, so the
      (*reset_cmd) function pointer is there to stay.
      
      However let's simplify the prototype and give it a struct dsa_switch (we
      want to avoid forward-declarations of structures, in this case struct
      sja1105_private, wherever we can).
      Signed-off-by: default avatarVladimir Oltean <olteanv@gmail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      abfb228a
    • David S. Miller's avatar
      Merge branch 'PTP-clock-source-for-SJA1105-tc-taprio-offload' · ccb68993
      David S. Miller authored
      Vladimir Oltean says:
      
      ====================
      PTP clock source for SJA1105 tc-taprio offload
      
      This series makes the IEEE 802.1Qbv egress scheduler of the sja1105
      switch use a time reference that is synchronized to the network. This
      enables quite a few real Time Sensitive Networking use cases, since in
      this mode the switch can offer its clients a TDMA sort of access to the
      network, and guaranteed latency for frames that are properly scheduled
      based on the common PTP time.
      
      The driver needs to do a 2-part activity:
      - Program the gate control list into the static config and upload it
        over SPI to the switch (already supported)
      - Write the activation time of the scheduler (base-time) into the
        PTPSCHTM register, and set the PTPSTRTSCH bit.
      - Monitor the activation of the scheduler at the planned time and its
        health.
      
      Ok, 3 parts.
      
      The time-aware scheduler cannot be programmed to activate at a time in
      the past, and there is some logic to avoid that.
      
      PTPCLKCORP is one of those "black magic" registers that just need to be
      written to the length of the cycle. There is a 40-line long comment in
      the second patch which explains why.
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ccb68993