- 28 Nov, 2018 12 commits
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Nicholas Kazlauskas authored
Modern display hardware is capable of supporting variable refresh rates. This patch introduces the "vrr_capable" property on the connector to allow userspace to query support for variable refresh rates. Atomic drivers should attach this property to connectors that are capable of driving variable refresh rates using drm_connector_attach_vrr_capable_property(). The value should be updated based on driver and hardware capability by using drm_connector_set_vrr_capable_property(). Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Oak Zeng authored
Move doorbell structures, enum definitions and helper functions from amdgpu.h to amdgpu_doorbell.h. No functional change Signed-off-by:
Oak Zeng <ozeng@amd.com> Proposed-by:
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Oak Zeng authored
ASIC specific doorbell layout is used instead of enum definition Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Suggested-by:
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Oak Zeng authored
Also call functioin amdgpu_device_doorbell_init after amdgpu_device_ip_early_init because the former depends on the later to set up asic-specific init_doorbell_index function Signed-off-by:
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Oak Zeng authored
This introduces new doorbell layout for vega20 and future asics v2: Use enum definition instead of hardcoded value Signed-off-by:
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Oak Zeng authored
Initialize doorbell index for asics vi and cik v2: Use enum definition instead of hardcoded number Signed-off-by:
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Oak Zeng authored
v2: Use enum definition instead of hardcoded value v3: Remove unused enum definition Signed-off-by:
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Oak Zeng authored
This is preparation to move doorbell index initialization to amdgpu_asic_funcs Signed-off-by:
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Oak Zeng authored
This is a preparation work to make reserved doorbell index per device, instead of using a global macro definition. By doing this, we can easily change doorbell layout for future ASICs while not affecting ASICs in production. Signed-off-by:
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David Francis authored
The fallback code for getting default backlight caps was using the wrong variable name. Fix it. Fixes: https://lists.freedesktop.org/archives/dri-devel/2018-November/197752.htmlSigned-off-by:
David Francis <David.Francis@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] Two non-blocking commits in succession can result in a sequence where the same dc->current_state is queried for both commits. 1. 1st commit -> check -> commit -> swaps atomic state -> queues work 2. 2nd commit -> check -> commit -> swaps atomic state -> queues work 3. 1st commit work finishes The issue with this sequence is that the same dc->current_state is read in both atomic checks. If the first commit modifies streams or planes those will be missing from the dc->current_state for the second atomic check. This result in many stream and plane errors in atomic commit tail. [How] The driver still needs to track old to new state to determine if the commit in its current implementation. Updating the dc_state in atomic tail is wrong since the dc_state swap should be happening as part of drm_atomic_helper_swap_state *before* the worker queue kicks its work off. The simplest replacement for the subclassing (which doesn't properly manage the old to new atomic state swap) is to use the drm private object helpers. While some of the dc_state members could be merged into dm_crtc_state or dm_plane_state and copied over that way it is easier for now to just treat the whole dc_state structure as a single private object. This allows amdgpu_dm to drop the dc->current_state copy from within atomic check. It's replaced by a copy from the current atomic state which is propagated correctly for the sequence described above. Since access to the dm_state private object is now locked this should also fix issues that could arise if submitting non-blocking commits from different threads. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Signed-off-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Christian König authored
This reverts commit 0efd2d2f. It's still causing problems for V3D. v2: keep rearming the timeout. Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
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- 26 Nov, 2018 14 commits
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Colin Ian King authored
There is a spelling mistake in the module description text and a comment too, fix them. Also line break overly long comment. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Brajeswar Ghosh authored
Remove dce/dce_mem_input.h which is included more than once Signed-off-by:
Brajeswar Ghosh <brajeswar.linux@gmail.com> Signed-off-by:
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Brajeswar Ghosh authored
Remove gca/gfx_8_0_enum.h which is included more than once Signed-off-by:
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Brajeswar Ghosh authored
Remove drm/drm_fb_helper.h which is included more than once Signed-off-by:
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David Francis authored
ACPI ATIF has a function called query backlight transfer characteristics. Among the information returned by this function is the minimum and maximum input signals for the backlight Call that function on ACPI init. When DM backlight device is updated, copy over the backlight caps into DM, but only once. Use the backlight caps in the backlight-to-dc calculation Signed-off-by:
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David Francis authored
The ACPI interface in AMD was a few years out of date and contained some unused and deprecated functions Remove functions: Select Active Displays, Get Lid State, Get TV Standard, Set TV Standard, Get Panel Expansion Mode, Set Panel Expansion Mode, Get Graphics Device Types Add functions: Query Backlight Transfer Characteristics, Ready To Undock Notification Changed functions: Get System Parameters, Get System BIOS Requests All changes are right from the standard ATI ACPI Control Methods V0.44 Signed-off-by:
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David Francis authored
Adaptive Backlight Management (ABM) is a feature that reduces backlight level to save power, while increasing pixel contrast and pixel luminance to maintain readability and image quality. ABM will adjust in response to the pixel luminance of the displayed content. ABM is made available as a drm property on eDP monitors called "abm level", which ranges from 0 to 4. When this property is set to 0, ABM is off. Levels 1 to 4 represent different ranges of backlight reduction. At higher levels both the backlight reduction and pixel adjustment will be greater. ABM requires DMCU firmware, which is currently available for Raven ASICs only. If the feature does not work, please ensure your firmware is up to date. v2: Fix commit message, only attach property if DMCU loaded v3: Store ABM level in crtc state to accommodate dc v4: Fix ABM saving on dpms cycle Signed-off-by:
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David Francis authored
DMCU IRAM must be loaded by the driver before DMCU can function. Move the IRAM code out of the shadows and into a new file modules/power/power_helpers.c The IRAM table contains the backlight curve and ABM parameters Add this new file to the Makefiles Call dmcu_load_iram in late init of DM Move struct dmcu_version from dc.h to dmcu.h to allow dmcu to be included on its own Signed-off-by:
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Rex Zhu authored
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c:49 amdgpu_allocate_static_csa() error: uninitialized symbol 'ptr'. the test if (!bo) doesn't work, as the bo is a pointer to a pointer. if bo create failed, the *bo will be set to NULL. so change to test *bo. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Guttula, Suresh authored
We observe black lines (underflow) on display when playing a 4K video with UVD. On Disabling Low memory P state this issue is not seen. In this patch ,disabling low memory P state only when video size >= 4k. Multiple runs of power measurement shows no impact Signed-off-by:
suresh guttula <suresh.guttula@amd.com> Reviewed-by:
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Guttula, Suresh authored
Add hwmgr callback "update_nbdpm_pstate".This will use to access "cz_nbdpm_pstate_enable_disable" function to enable/disable low memory pstate. Signed-off-by:
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Shirish S authored
This reverts commit dbd8299c32f6f413f6cfe322fe0308f3cfc577e8. Reason for revert: This patch sends msg PPSMC_MSG_DisableLowMemoryPstate(0x002e) in wrong of sequence to SMU which is before PPSMC_MSG_UVDPowerON (0x0008). This leads to SMU failing to service the request as it is dependent on UVD to be powered ON, since it accesses UVD registers. This msg should ideally be sent only when the UVD is about to decode a 4k video. Signed-off-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
Before: We use drm_match_cea_mode() to get the vic for any mode we want to set, most of the time vic will be different for the new mode. DC uses memcmp to check if timing changed, in this case DC will say timing changed and we endup doing a full modeset. Current: Now we check if !RMX_OFF and old_refresh == new_refresh if so we copy the vic from old timing. In a case where we are currently on a lower timing and want to change to higher mode, stream->dst will be different and cause us to do a full modeset, which is what we want. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
Setting this allows for display scaling by default Signed-off-by:
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- 21 Nov, 2018 5 commits
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Colin Ian King authored
Currently there are several instances of pointer fs_params being dereferenced before fs_params is being null checked. Fix this by only dereferencing fs_params after the null check. Detected by CoverityScan, CID#1475565 ("Dereference before null check") Fixes: e1e8a020 ("drm/amd/display: Add support for Freesync 2 HDR and Content to Display Mapping") Signed-off-by: -
Brajeswar Ghosh authored
Remove dm_services_types.h which is included more than once Signed-off-by:
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Brajeswar Ghosh authored
Remove gca/gfx_8_0_sh_mask.h which is included more than once Signed-off-by:
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Brajeswar Ghosh authored
Remove gca/gfx_8_0_d.h which is included more than once Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Philip Yang authored
Based SDMA fw version to enable has_page_queue support. Have to move sdma_v4_0_init_microcode from sw_init to early_init, to load firmware and init fw_version before set_ring/buffer/vm_pte_funcs use it. v2: don't enable on vega12, 20 until confirmed Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Acked-by:
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- 20 Nov, 2018 8 commits
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Philip Yang authored
Because increase SDMA_DOORBELL_RANGE to add new SDMA doorbell for paging queue will break SRIOV, instead we can reserve and map two doorbell pages for amdgpu, paging queues doorbell index use same index as SDMA gfx queues index but on second page. For Vega20, after we change doorbell layout to increase SDMA doorbell for 8 SDMA RLC queues later, we could use new doorbell index for paging queue. Signed-off-by:
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Philip Yang authored
This looks like copy paste typo Signed-off-by:
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Rex Zhu authored
The static struct drm_driver *driver was not used because drm_pci_init was deprecated v2: Remove static pointer pdriver(Christian) Reviewed-by:
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Eric Huang authored
It is to improve system limit by: 1. replacing userptrlimit with a total memory limit that conunts TTM memory usage and userptr usage. 2. counting acc size for all BOs. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Felix Kuehling authored
This change prepares for adding SG BOs that will be used for mapping doorbells into GPUVM address space. This type of BO would be mistaken for an invalid userptr BO. Improve that check to test that it's actually a userptr BO so that SG BOs that are still in the CPU domain can be validated and mapped correctly. Signed-off-by:
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Felix Kuehling authored
The adev parameter in amdgpu_sync_fence and amdgpu_sync_resv is only needed for updating sync->last_vm_update. This breaks if different adevs are passed to calls for the same sync object. Always pass NULL for calls from KFD because sync objects used for KFD don't belong to any particular device, and KFD doesn't need the sync->last_vm_update fence. This fixes kernel log warnings on multi-GPU systems after recent changes in amdgpu_amdkfd_gpuvm_restore_process_bos. Signed-off-by:
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Harish Kasiviswanathan authored
Instead of waiting for each KFD BO after validation just wait for the last BO moving fence. Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
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Harish Kasiviswanathan authored
PD or PT might have to be moved during validation and this move has to be completed before updating it. If page table updates are done using SDMA then this serializing is done by SDMA command submission. And if PD/PT updates are done by CPU, then explicit waiting for PD/PT updates are done in amdgpu VM amdgpu_vm_wait_pd function. Sync to PD BO moving fence to handle corner case where none of the PTs are updated but PD is evicted. Signed-off-by:
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- 19 Nov, 2018 1 commit
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Brajeswar Ghosh authored
Remove gca/gfx_8_0_enum.h which is included more than once Signed-off-by:
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