- 31 Jul, 2019 40 commits
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Evan Quan authored
Support sensor reading for gpu loading, power and temperatures. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
Initialize arcturus SMU metrics table. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
VCN should be used for Vega20 later ASICs while UVD and VCE are for previous ASICs. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
No VCN DPM bit check as that's different from VCN PG. Also no extra check for possible double enablement/disablement as that's already done by VCN. v2: check return value of smu_feature_set_enabled Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
Commonly used for VCN powergate status retrieval for SW SMU. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
Enable VCN powergate status report on Raven. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
VCN is widely used in new ASICs and different from tranditional UVD and VCE. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Le Ma authored
Update for sdma ras ecc_irq and other minors. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Le Ma authored
Arcturus has different _BASE_IDX value in some HWIP_offset.h. To make source files like smu_v11_0.c and soc15.c that include HWIP_offset.h of Vega20 reusable for Arcturus, align this base offset with Vega20. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
As for now, only "Prefetcher" is guarded to be working from SMU firmware. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
Arcturus VCN should powergate in the way as Navi. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
Arcturus powerplay is ready to use. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
Initialize base address for those IPs which are used in powerplay. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
Enable arcturus SW SMU routines. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
Arcturus ASIC specific powerplay interfaces. V2: correct SMU msg naming drop unnecessary debugs V3: rebase (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
Correct header and fix typo. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
It guides how driver should interface with SMU in arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
This is especially useful in early bring up phase. v2: disabled by default (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
New smcdpminfo table used in arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Jay Cornwall authored
VCC moved out of user SGPR allocation in gfx10. It's now stored in SGPRs 106-107. Also fixes incorrect SGPR read offsets. Cc: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: shaoyunl <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Jay Cornwall authored
These moved from SGPRs in gfx9 to HWREG in gfx10. Cc: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: shaoyunl <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Jay Cornwall authored
Copy/paste error, first 4 VGPRs are separated by 64 dwords (256 bytes). Cc: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: shaoyunl <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
[Why] We were previously forcing the uclk for every state to max and reducing the switch time to prevent uclk switching from occuring. This workaround was previously needed in order to avoid hangs + underflow under certain display configurations. Now that DC has the proper fix complete we can drop the hacks and improve power for most display configurations. [How] We still need the function pointers hooked up to grab the real uclk states from pplib. The rest of the prior hack can be reverted. The key requirements here are really just DC support, updated firmware, and support for disabling p-state support when needed in pplib/smu. When these requirements are met uclk switching works without underflow or hangs. Fixes: 02316e96 ("drm/amd/display: Force uclk to max for every state") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
[Why] In order to support uclk switching on NV10 the SOC bounding box needs to be updated. [How] We currently read the constants from the gpu info FW, but supporting workarounds in DC for different versions of the FW adds additional complexity to the codebase. NV10 has been released so it's cleanest to keep the bounding box and source code in sync by embedding the bounding box like we do for other ASICs. Fixes: 02316e96 ("drm/amd/display: Force uclk to max for every state") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Wang Xiayang authored
Coccinelle reports a path that the array "data" is never initialized. The path skips the checks in the conditional branches when either of callback functions, read_wave_vgprs and read_wave_sgprs, is not registered. Later, the uninitialized "data" array is read in the while-loop below and passed to put_user(). Fix the path by allocating the array with kcalloc(). The patch is simplier than adding a fall-back branch that explicitly calls memset(data, 0, ...). Also it does not need the multiplication 1024*sizeof(*data) as the size parameter for memset() though there is no risk of integer overflow. Signed-off-by: Wang Xiayang <xywang.sjtu@sjtu.edu.cn> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
We always need to drop the ctx reference and should check for errors first and then dereference the fence pointer. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Kenneth Feng authored
provide the interface for DAL to disable uclk switch on navi10. in this case, the uclk will be fixed to maximum. this is a workaround when display configuration causes underflow issue. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Thong Thai authored
VCN 2.0 firmware now requires a packet start command to be sent before any other decode ring buffer command. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Updated settings for hw team. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Kevin Wang authored
1. Unified feature enable status format in sysfs 2. Rename ppfeature to pp_features to adapt other pp sysfs node name 3. this function support all asic, not asic related function. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Acked-by: Rui Huang <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Kevin Wang authored
this function is not ip or asic related function, so move it to top level as public api in smu. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Kevin Wang authored
add smu_get_feature_name support in smu. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Kevin Wang authored
add smu_get_message_name support in smu. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Kevin Wang authored
move some enum type (message, feature, clock) to smu_types.h. these types is too long in amdgpu_smu.h, and not clearly. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Joseph Greathouse authored
Units in the GDS block default to allowing all VMIDs access to all entries. Disable shader access to the GDS, GWS, and OA blocks from all compute and gfx VMIDs by default. For compute, HWS firmware will set up the access bits for the appropriate VMID when a compute queue requires access to these blocks. The driver will handle enabling access on-demand for graphics VMIDs. Leaving VMID0 with full access because otherwise HWS cannot save or restore values during task switch. v2: Fixed code and comment styling. Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Thong Thai authored
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This bit was previously set by the RBC HW on older firmware. Newer firmware uses a SW RBC and this bit has to be set by the driver. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Some code was missing the CONFIG_DRM_AMD_DC_DSC_SUPPORT guard. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Andrey Grodzovsky authored
Add restriction to dissallow GTT domain if the relevant BO doesn't have USWC flag set to avoid the APU hang scenario. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
The PCI revision id determines the sku. Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
When doing a GPU reset or unloading the driver, we need to put the SMU into the apprpriate state for the re-init after the reset or unload to reliably work. I don't think this is necessary for BACO because the SMU actually controls the BACO state to it needs to be active. For suspend (S3), the asic is put into D3 so the SMU would be powered down so I don't think we need to put the SMU into any special state. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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