- 22 Mar, 2022 3 commits
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Palmer Dabbelt authored
Add support for RSEQ, restartable sequences, for RISC-V. This also adds support for the related selftests. Note: the selftests require a linker with 3e7bd7f2414 ("RISC-V: Fix linker problems with tls copy relocs."), which was first released in 2.33 (from 2019). * palmer/riscv-rseq: rseq/selftests: Add support for RISC-V RISC-V: Add support for restartable sequence -
Vincent Chen authored
Add support for RISC-V in the rseq selftests, which covers both 64-bit and 32-bit ISA with little endian mode. Signed-off-by:
Vincent Chen <vincent.chen@sifive.com> Tested-by:
Eric Lin <eric.lin@sifive.com> Reviewed-by:
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by:
Palmer Dabbelt <palmer@rivosinc.com>
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Vincent Chen authored
Add calls to rseq_signal_deliver() and rseq_syscall() to introduce RSEQ support. 1. Call the rseq_signal_deliver() function to fixup on the pre-signal frame when a signal is delivered on top of a restartable sequence critical section. 2. Check that system calls are not invoked from within rseq critical sections by invoking rseq_signal() from ret_from_syscall(). With CONFIG_DEBUG_RSEQ, such behavior results in termination of the process with SIGSEGV. Signed-off-by:
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- 21 Mar, 2022 10 commits
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Palmer Dabbelt authored
This series improves perf support for RISC-V based system using SBI PMU and Sscofpmf extensions, by adding a new generic RISC-V perf framework along with a pair of drivers: one that usese the new performance-monitoring extensions and one that keeps support for the existing systems that only have the legacy counters. Tested-by:Nikita Shubin <n.shubin@yadro.com> * palmer/riscv-pmu: MAINTAINERS: Add entry for RISC-V PMU drivers Documentation: riscv: Remove the old documentation RISC-V: Add sscofpmf extension support RISC-V: Add perf platform driver based on SBI PMU extension RISC-V: Add RISC-V SBI PMU extension definitions RISC-V: Add a simple platform driver for RISC-V legacy perf RISC-V: Add a perf core library for pmu drivers RISC-V: Add CSR encodings for all HPMCOUNTERS RISC-V: Remove the current perf implementation
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Atish Patra authored
Add myself and Anup as maintainer for RISC-V PMU drivers. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Signed-off-by:
Atish Patra <atishp@rivosinc.com> Signed-off-by:
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Atish Patra authored
The existing pmu documentation describes the limitation of perf infrastructure in RISC-V ISA and limited feature set of perf in RISC-V. However, SBI PMU extension and sscofpmf extension(ISA extension) allows to implement most of the required features of perf. Remove the old documentation which is not accurate anymore. Reviewed-by:
Anup Patel <anup@brainfault.org> Signed-off-by:
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Atish Patra authored
The sscofpmf extension allows counter overflow and filtering for programmable counters. Enable the perf driver to handle the overflow interrupt. The overflow interrupt is a hart local interrupt. Thus, per cpu overflow interrupts are setup as a child under the root INTC irq domain. Signed-off-by:
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Atish Patra authored
RISC-V SBI specification added a PMU extension that allows to configure start/stop any pmu counter. The RISC-V perf can use most of the generic perf features except interrupt overflow and event filtering based on privilege mode which will be added in future. It also allows to monitor a handful of firmware counters that can provide insights into firmware activity during a performance analysis. Signed-off-by:
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Atish Patra authored
This patch adds all the definitions defined by the SBI PMU extension. Reviewed-by:
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Atish Patra authored
The old RISC-V perf implementation allowed counting of only cycle/instruction counters using perf. Restore that feature by implementing a simple platform driver under a separate config to provide backward compatibility. Any existing software stack will continue to work as it is. However, it provides an easy way out in future where we can remove the legacy driver. Reviewed-by:
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Atish Patra authored
Implement a perf core library that can support all the essential perf features in future. It can also accommodate any type of PMU implementation in future. Currently, both SBI based perf driver and legacy driver implemented uses the library. Most of the common perf functionalities are kept in this core library wile PMU specific driver can implement PMU specific features. For example, the SBI specific functionality will be implemented in the SBI specific driver. Reviewed-by:
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Atish Patra authored
Linux kernel can directly read these counters as the HPMCOUNTERS CSRs are accessible in S-mode. Reviewed-by:
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Atish Patra authored
The current perf implementation in RISC-V is not very useful as it can not count any events other than cycle/instructions. Moreover, perf record can not be used or the events can not be started or stopped. Remove the implementation now for a better platform driver in future that will implement most of the missing functionality. Reviewed-by:
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- 17 Mar, 2022 7 commits
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Palmer Dabbelt authored
This series implements a generic framework to parse multi-letter ISA extensions. * palmer/riscv-isa: RISC-V: Improve /proc/cpuinfo output for ISA extensions RISC-V: Do no continue isa string parsing without correct XLEN RISC-V: Implement multi-letter ISA extension probing framework RISC-V: Extract multi-letter extension names from "riscv, isa" RISC-V: Minimal parser for "riscv, isa" strings RISC-V: Correctly print supported extensions
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Atish Patra authored
Currently, the /proc/cpuinfo outputs the entire riscv,isa string which is not ideal when we have multiple ISA extensions present in the ISA string. Some of them may not be enabled in kernel as well. Same goes for the single letter extensions as well which prints the entire ISA string. Some of they may not be valid ISA extensions as well (e.g 'su') Parse only the valid & enabled ISA extension and print them. Tested-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
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Atish Patra authored
The isa string should begin with either rv64 or rv32. Otherwise, it is an incorrect isa string. Currently, the string parsing continues even if it doesnot begin with current XLEN. Fix this by checking if it found "rv64" or "rv32" in the beginning. Tested-by:
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Atish Patra authored
Multi-letter extensions can be probed using exising riscv_isa_extension_available API now. It doesn't support versioning right now as there is no use case for it. Individual extension specific implementation will be added during each extension support. Tested-by:
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Tsukasa OI authored
Currently, there is no usage for version numbers in extensions as any ratified non base ISA extension will always at v1.0. Extract the extension names in place for future parsing. Tested-by:
Tsukasa OI <research_trasio@irq.a4lg.com> [Improved commit text and comments] Signed-off-by:
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Tsukasa OI authored
Current hart ISA ("riscv,isa") parser don't correctly parse: 1. Multi-letter extensions 2. Version numbers All ISA extensions ratified recently has multi-letter extensions (except 'H'). The current "riscv,isa" parser that is easily confused by multi-letter extensions and "p" in version numbers can be a huge problem for adding new extensions through the device tree. Leaving it would create incompatible hacks and would make "riscv,isa" value unreliable. This commit implements minimal parser for "riscv,isa" strings. With this, we can safely ignore multi-letter extensions and version numbers. [Improved commit text and fixed a bug around 's' in base extension] Signed-off-by: -
Tsukasa OI authored
This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Reviewed-by:
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- 10 Mar, 2022 13 commits
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Michael T. Kloos authored
Rewrote the RISC-V memmove() assembly implementation. The previous implementation did not check memory alignment and it compared 2 pointers with a signed comparison. The misaligned memory access would cause the kernel to crash on systems that did not emulate it in firmware and did not support it in hardware. Firmware emulation is slow and may not exist. The RISC-V spec does not guarantee that support for misaligned memory accesses will exist. It should not be depended on. This patch now checks for XLEN granularity of co-alignment between the pointers. Failing that, copying is done by loading from the 2 contiguous and naturally aligned XLEN memory locations containing the overlapping XLEN sized data to be copied. The data is shifted into the correct place and binary or'ed together on each iteration. The result is then stored into the corresponding naturally aligned XLEN sized location in the destination. For unaligned data at the terminations of the regions to be copied or for copies less than (2 * XLEN) in size, byte copy is used. This patch also now uses unsigned comparison for the pointers and migrates to the newer assembler annotations from the now deprecated ones. Signed-off-by:
Michael T. Kloos <michael@michaelkloos.com> Signed-off-by:
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Palmer Dabbelt authored
This series updates the Microchip Icicle Kit device tree by adding a host of peripherals, and some updates to the memory map. In addition, the device tree has been split into a third part, which contains "soft" peripherals that are in the fpga fabric. Several of the entries are for peripherals that have not get had their drivers upstreamed, so in those cases the dt bindings are included where appropriate in order to avoid the many "DT compatible string <x> appears un-documented" errors. * palmer/riscv-microchip: MAINTAINERS: update riscv/microchip entry riscv: dts: microchip: add new peripherals to icicle kit device tree riscv: dts: microchip: update peripherals in icicle kit device tree riscv: dts: microchip: refactor icicle kit device tree riscv: dts: microchip: add fpga fabric section to icicle kit riscv: dts: microchip: use clk defines for icicle kit dt-bindings: pwm: add microchip corepwm binding dt-bindings: gpio: add bindings for microchip mpfs gpio dt-bindings: rtc: add bindings for microchip mpfs rtc dt-bindings: soc/microchip: add info about services to mpfs sysctrl dt-bindings: soc/microchip: update syscontroller compatibles dt-bindings: clk: microchip: Add Microchip PolarFire host binding
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Conor Dooley authored
Update the RISC-V/Microchip entry by adding the microchip dts directory and myself as maintainer Reviewed-by:
Lewis Hanly <lewis.hanly@microchip.com> Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Acked-by:
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Conor Dooley authored
Add new peripherals to the MPFS, and enable them in the Icicle kit device tree: 2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller, USB host & system controller. Signed-off-by:
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Conor Dooley authored
Assorted minor changes to the MPFS/Icicle kit device tree: - enable mmuart4 instead of mmuart0 - remove sifive pdma - split memory node to match updated fpga design - move stdout path to serial1 to avoid collision with bootloader running on the e51 Signed-off-by: -
Conor Dooley authored
Assorted minor changes to the MPFS/Icicle kit device tree: - rename serial to mmuart to match microchip documentation - move phy0 inside mac1 node to match phy configuration - add labels where missing (cpus, cache controller) - add missing address cells & interrupts to MACs Signed-off-by:
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Conor Dooley authored
Split the device tree for the Microchip MPFS into two sections by adding microchip-mpfs-fabric.dtsi, which contains peripherals contained in the FPGA fabric. Signed-off-by:
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Conor Dooley authored
Update the Microchip Icicle kit device tree by replacing clock related magic numbers with their defined counterparts. Signed-off-by:
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Conor Dooley authored
Add device tree bindings for the Microchip fpga fabric based "core" PWM controller. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Uwe Kleine-K=F6nig <u.kleine-koenig@pengutronix.de> Acked-by:
Thierry Reding <thierry.reding@gmail.com> Signed-off-by:
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Conor Dooley authored
Add device tree bindings for the gpio controller on the Microchip PolarFire SoC. Reviewed-by:
Bartosz Golaszewski <brgl@bgdev.pl> Signed-off-by:
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Conor Dooley authored
Add device tree bindings for the real time clock on the Microchip PolarFire SoC. Signed-off-by:
Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
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Conor Dooley authored
The services actually provided by the system controller are not documented so add some words about what the system controller can actually do. Add a link to the oneline documentation with the specific details of each individual service. Also, drop the unneeded label from the example. Signed-off-by:
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Conor Dooley authored
The Polarfire SoC is currently using two different compatible string prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in its system controller in order to match the compatible string used in the soc binding and device tree Reviewed-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
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- 23 Feb, 2022 1 commit
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Mayuresh Chitale authored
Enabling hugetlbfs in the defconfigs to allow tuning KVM guest performance using huge pages. Signed-off-by:
Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by:
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- 22 Feb, 2022 1 commit
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Palmer Dabbelt authored
This implements Sv57 support at runtime. The kernel will try to boot with 5-level page table firstly , and will fallback to 4-level if the HW does not support it. And it will finally fallback to 3-level if the HW alse does not support sv48. * riscv-sv57: riscv: mm: Support kasan for sv57 riscv: mm: Set sv57 on defaultly riscv: mm: Prepare pt_ops helper functions for sv57 riscv: mm: Control p4d's folding by pgtable_l5_enabled
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- 15 Feb, 2022 4 commits
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Qinglin Pan authored
This patchset add kasan_populate and kasan_shallow_populate for sv57, and is tested on both qemu and unmatched with CONFIG_KASAN and CONFIG_KASAN_VMALLOC on. Signed-off-by:
Qinglin Pan <panqinglin2020@iscas.ac.cn> Signed-off-by:
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Qinglin Pan authored
This patch sets sv57 on defaultly if CONFIG_64BIT. And do fallback to try to set sv48 on boot time if sv57 is not supported in current hardware. Signed-off-by:
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Qinglin Pan authored
This patch prepare some pt_ops helper functions which will be used in creating sv57 mappings during boot time. Signed-off-by:
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Qinglin Pan authored
To determine pgtable level at boot time, we can not use helper functions in include/asm-generic/pgtable-nop4d.h and must implement these functions. This patch uses pgtable_l5_enabled variable instead of including pgtable-nop4d.h to controle p4d's folding, and implements corresponding helper functions. Signed-off-by:
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- 14 Feb, 2022 1 commit
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Jisheng Zhang authored
satp_mode is never modified after init, so it can be marked as __ro_after_init. Signed-off-by:
Jisheng Zhang <jszhang@kernel.org> Signed-off-by:
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