- 16 Jul, 2024 2 commits
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Stephen Boyd authored
* clk-renesas: clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C clk: renesas: r8a779h0: Add Audio clocks clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP dt-bindings: clock: rcar-gen2: Remove obsolete header files dt-bindings: clock: r8a7779: Remove duplicate newline clk: renesas: Drop "Renesas" from individual driver descriptions clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments clk: renesas: r8a779h0: Add VIN clocks dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock clk: renesas: r8a77970: Use common cpg_lock clk: renesas: r8a779h0: Add CSI-2 clocks clk: renesas: r8a779h0: Add ISPCS clocks * clk-amlogic: clk: meson: add missing MODULE_DESCRIPTION() macros dt-bindings: clock: meson: a1: peripherals: support sys_pll input dt-bindings: clock: meson: a1: pll: introduce new syspll bindings clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL clk: meson: c3: add c3 clock peripherals controller driver clk: meson: c3: add support for the C3 SoC PLL clock dt-bindings: clock: add Amlogic C3 peripherals clock controller dt-bindings: clock: add Amlogic C3 SCMI clock controller support dt-bindings: clock: add Amlogic C3 PLL clock controller dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format clk: meson: s4: fix pwm_j_div parent clock clk: meson: s4: fix fixed_pll_dco clock * clk-allwinner: clk: sunxi-ng r40: Constify struct regmap_config clk: sunxi-ng: h616: Add clock/reset for GPADC dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks clk: sunxi: Remove unused struct 'gates_data' clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros * clk-samsung: clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical clk: samsung: Switch to use kmemdup_array() clk: samsung: exynos-clkout: Remove misleading of_match_table/MODULE_DEVICE_TABLE
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Stephen Boyd authored
- Add reset support to Airoha EN7581 clk driver - Add module description to mediatek clk drivers * clk-stm: clk: stm32mp25: add security clocks clk: stm32mp2: use of STM32 access controller * clk-cleanup: clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate() clk: lpc32xx: Constify struct regmap_config clk: xilinx: Constify struct regmap_config dt-bindings: clock: sprd,sc9860-clk: convert to YAML dt-bindings: clock: qoriq-clock: convert to yaml format clk: vexpress-osc: add missing MODULE_DESCRIPTION() macro clk: sifive: prci: fix module autoloading dt-bindings: clock: milbeaut: Drop providers and consumers from example clk: sprd: add missing MODULE_DESCRIPTION() macro clk: sophgo: add missing MODULE_DESCRIPTION() macro * clk-kunit: clk: disable clk gate tests for s390 clk: test: add missing MODULE_DESCRIPTION() macros * clk-mediatek: clk: en7523: fix rate divider for slic and spi clocks clk: en7523: Remove PCIe reset open drain configuration for EN7581 clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC clk: en7523: Add reset-controller support for EN7581 SoC dt-bindings: clock: airoha: Add reset support to EN7581 clock binding dt-bindings: clock: mediatek: Document reset cells for MT8188 sys clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys clk: mediatek: Add a module description where missing
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- 10 Jul, 2024 2 commits
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Thorsten Blum authored
Use clamp() instead of duplicating its implementation. Signed-off-by:
Thorsten Blum <thorsten.blum@toblux.com> Link: https://lore.kernel.org/r/20240710143309.706135-2-thorsten.blum@toblux.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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Javier Carrasco authored
`sun8i_r40_ccu_regmap_config` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by:
Javier Carrasco <javier.carrasco.cruz@gmail.com> Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-9-7d15a0671d6f@gmail.comReviewed-by:
Andre Przywara <andre.przywara@arm.com> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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- 08 Jul, 2024 12 commits
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Lorenzo Bianconi authored
Introduce div_offset field in en_clk_desc struct in order to fix rate divider estimation in en7523_get_div routine for slic and spi fixed rate clocks. Moreover, fix base_shift for crypto clock. Fixes: 1e627317 ("clk: en7523: Add clock driver for Airoha EN7523 SoC") Signed-off-by:
Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/c491bdea05d847f1f1294b94f14725d292eb95d0.1718615934.git.lorenzo@kernel.orgReviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by:
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Javier Carrasco authored
`lpc32xx_scb_regmap_config` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by:
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Javier Carrasco authored
`vcu_settings_regmap_config` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by:
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Lorenzo Bianconi authored
PCIe reset open drain configuration will be managed by pinctrl driver. Reviewed-by:
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Lorenzo Bianconi authored
Get rid of prepare and unpreare callbacks for PCIe clock since they can be modeled as a reset line cosumed by the PCIe driver (pcie-mediatek-gen3) Reviewed-by:
Zhengping Zhang <zhengping.zhang@airoha.com> Signed-off-by:
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Lorenzo Bianconi authored
Introduce reset API support to EN7581 clock driver. Reviewed-by:
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Lorenzo Bianconi authored
Introduce reset capability to EN7581 device-tree clock binding documentation. Add reset register mapping between misc scu and pb scu ones in order to follow the memory order. This change is not introducing any backward compatibility issue since the EN7581 dts is not upstream yet. Fixes: 0a382be0 ("dt-bindings: clock: airoha: add EN7581 binding") Reviewed-by:
Rob Herring (Arm) <robh@kernel.org> Signed-off-by:
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AngeloGioacchino Del Regno authored
The MT8188 sys clocks embed a reset controller: add #reset-cells to the binding to allow using resets. Fixes: 1086a531 ("dt-bindings: clock: mediatek: Add new MT8188 clock") Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Alper Nebi Yasak authored
The MT8173 infracfg clock driver does initialization in two steps, via a CLK_OF_DECLARE_DRIVER declaration. However its early init function doesn't get to run when it's built as a module, presumably since it's not loaded by the time it would have been called by of_clk_init(). This causes its second-step probe() to return -ENOMEM when trying to register clocks, as the necessary clock_data struct isn't initialized by the first step. MT2701 and MT6797 clock drivers also use this mechanism, but they try to allocate the necessary clock_data structure if missing in the second step. Mimic that for the MT8173 infracfg clock as well to make it work as a module. Signed-off-by:
Alper Nebi Yasak <alpernebiyasak@gmail.com> Link: https://lore.kernel.org/r/20240612201211.91683-1-alpernebiyasak@gmail.comReviewed-by:
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Christian Marangi authored
Add required syscon compatible for mt7622 pciesys. This is required for SATA interface as the regs are shared. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20240628105542.5456-2-ansuelsmth@gmail.comReviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Stanislav Jakubek authored
Convert the Spreadtrum SC9860 clock bindings to DT schema. Signed-off-by:
Stanislav Jakubek <stano.jakubek@gmail.com> Link: https://lore.kernel.org/r/ZobghvwZAyMjl4eB@standask-GA-A55M-S2HPReviewed-by:
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Frank Li authored
Convert qoria-clock DT binding to yaml format. Split to two files qoriq-clock.yaml and qoriq-clock-legancy.yaml. Addtional change: - Remove clock consumer part in example - Fixed example dts error - Deprecated legancy node - fsl,b4420-clockgen and fsl,b4860-clockgen fallback to fsl,b4-clockgen. Signed-off-by:
Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240701205809.1978389-1-Frank.Li@nxp.comReviewed-by:
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- 02 Jul, 2024 3 commits
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Jeff Johnson authored
With ARCH=arm64, make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/versatile/clk-vexpress-osc.o Add the missing invocation of the MODULE_DESCRIPTION() macro. Signed-off-by:
Jeff Johnson <quic_jjohnson@quicinc.com> Link: https://lore.kernel.org/r/20240613-md-arm64-drivers-clk-versatile-v1-1-6b8a5e5e00ef@quicinc.comAcked-by:
Sudeep Holla <sudeep.holla@arm.com> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Audra Mitchell authored
Currently clk-gate tests for s390 fail as the tests create a pretend clk-gate and use a "fake_reg" to emulate the expected behavior of the clk_gate->reg. I added some debug statements to the driver and noticed that the reg changes after initialization to -1, which is coming from an error coming from zpci_load(). This is likely because the test is using fake iomem and the s390 architecture likely isn't designed to handle that. Turn off the clk-gate tests for s390 for now as there is no clear work around for this problem as discussed in upstream conversation [1]. [1] https://lore.kernel.org/all/301cd41e6283c12ac67fb8c0f8d5c929.sboyd@kernel.org/T/#tSigned-off-by:
Audra Mitchell <audra@redhat.com> Link: https://lore.kernel.org/r/20240702125539.524489-1-audra@redhat.comSigned-off-by:
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Stephen Boyd authored
Merge tag 'samsung-clk-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung Pull Samsung SoC clk drivers updates from Krzysztof Kozlowski: - exynos-clkout: Remove usage of of_device_id table as .of_match_table, because the driver is instantiated as MFD cell, not as standalone platform driver. Populated .of_match_table confused people few times to convert the code to device_get_match_data(), which broke the driver. - Mark one of UFS clocks as critical, because having it off stops the system from shutdown - Use kmemdup_array() when applicable * tag 'samsung-clk-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical clk: samsung: Switch to use kmemdup_array() clk: samsung: exynos-clkout: Remove misleading of_match_table/MODULE_DEVICE_TABLE
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- 01 Jul, 2024 4 commits
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Stephen Boyd authored
Merge tag 'sunxi-clk-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner SoC clk driver updates from Chen-Yu Tsai: - Remove unused 'struct gates_data' from old sunxi driver library - Add missing MODULE_DESCRIPTION() macros for sunxi-ng drivers - Add GPADC clock and reset for H616 * tag 'sunxi-clk-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: h616: Add clock/reset for GPADC dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks clk: sunxi: Remove unused struct 'gates_data' clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros
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https://github.com/BayLibre/clk-mesonStephen Boyd authored
Pull Amlogic clock driver updates from Jerome Brunet: - Minor S4 clock fixes - DT bindings Yaml conversion of the AXG audio controller - C3 clock controllers support - Flag added to skip init of already enabled PLLs and avoid relocking - A1 DT bindings updates for system pll support - Add missing MODULE_DESCRIPTION where necessary. * tag 'clk-meson-v6.11-1' of https://github.com/BayLibre/clk-meson: clk: meson: add missing MODULE_DESCRIPTION() macros dt-bindings: clock: meson: a1: peripherals: support sys_pll input dt-bindings: clock: meson: a1: pll: introduce new syspll bindings clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL clk: meson: c3: add c3 clock peripherals controller driver clk: meson: c3: add support for the C3 SoC PLL clock dt-bindings: clock: add Amlogic C3 peripherals clock controller dt-bindings: clock: add Amlogic C3 SCMI clock controller support dt-bindings: clock: add Amlogic C3 PLL clock controller dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format clk: meson: s4: fix pwm_j_div parent clock clk: meson: s4: fix fixed_pll_dco clock
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Stephen Boyd authored
Merge tag 'renesas-clk-for-v6.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Remove obsolete clock DT binding header files - Add Battery Backup (VBATTB) and I2C clocks, resets, and power domains on RZ/G3S - Add audio clocks on R-Car V4M - Add video capture (ISPCS, CSI-2, VIN) clocks on R-Car V4M - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C clk: renesas: r8a779h0: Add Audio clocks clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP dt-bindings: clock: rcar-gen2: Remove obsolete header files dt-bindings: clock: r8a7779: Remove duplicate newline clk: renesas: Drop "Renesas" from individual driver descriptions clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments clk: renesas: r8a779h0: Add VIN clocks dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock clk: renesas: r8a77970: Use common cpg_lock clk: renesas: r8a779h0: Add CSI-2 clocks clk: renesas: r8a779h0: Add ISPCS clocks
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Peter Griffin authored
The system hangs on poweroff when this UFS clock is turned off, meaning the system never powers down. For the moment mark the clock as critical. Reviewed-by:
Will McVicker <willmcvicker@google.com> Tested-by:
Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20240628223506.1237523-5-peter.griffin@linaro.orgSigned-off-by:
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- 27 Jun, 2024 3 commits
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Claudiu Beznea authored
Add clock, reset and power domain support for the I2C channels available on the Renesas RZ/G3S SoC. Signed-off-by:
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240625121358.590547-2-claudiu.beznea.uj@bp.renesas.comSigned-off-by:
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Kuninori Morimoto authored
Add module clocks for the Audio (SSI/SSIU) blocks on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by:
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Claudiu Beznea authored
The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB) that generates the RTC clock. Add clock, reset and power domain support for it. Signed-off-by:
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- 24 Jun, 2024 4 commits
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Geert Uytterhoeven authored
The clock definitions in <dt-bindings/clock/r8a779?-clock.h> were superseded by those in <dt-bindings/clock/r8a779?-cpg-mssr.h> a long time ago. The last DTS user of these files was removed in commit 362b334b ("ARM: dts: r8a7791: Convert to new CPG/MSSR bindings") in v4.15. Driver support for the old bindings was removed in commit 58256143 ("clk: renesas: Remove R-Car Gen2 legacy DT clock support") in v5.5, so there is no point to keep on carrying these. Signed-off-by:
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Marek Vasut authored
Drop duplicate newline. No functional change. Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by:
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Geert Uytterhoeven authored
All configuration options are under the big "Renesas SoC clock support" umbrella, so there is no reason to repeat this for each driver. Hence drop "Renesas" from the few that do. Signed-off-by:
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Geert Uytterhoeven authored
The multipliers for PLL2 and PLL4 as listed in the comments for the cpg_pll_configs[] array are incorrect. Fix them. Note that the actual values in the tables were correct. Fixes: f077cab3 ("clk: renesas: cpg-mssr: Add support for R-Car V4M") Reported-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/07126b55807c1596422c9547e72f0a032487da1e.1718177076.git.geert+renesas@glider.be
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- 22 Jun, 2024 3 commits
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Chris Morgan authored
Add the GPADC required clock and reset which is used for the onboard GPADC. Signed-off-by:
Chris Morgan <macromorgan@hotmail.com> Acked-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by:
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Chen-Yu Tsai authored
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Chris Morgan authored
Add the required clock bindings for the GPADC. Signed-off-by:
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- 16 Jun, 2024 1 commit
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Andy Shevchenko authored
Let the kememdup_array() take care about multiplication and possible overflows. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20240606161028.2986587-4-andriy.shevchenko@linux.intel.comSigned-off-by:
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- 14 Jun, 2024 1 commit
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Jerome Brunet authored
Add the missing MODULE_DESCRIPTION() in the Amlogic clock modules missing it. Reported-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240611133512.341817-1-jbrunet@baylibre.comSigned-off-by:
Jerome Brunet <jbrunet@baylibre.com>
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- 11 Jun, 2024 2 commits
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Niklas Söderlund authored
Add the VIN module clocks, which are used by the VIN modules on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by:
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Lad Prabhakar authored
For the RZ/G2L and similar SoCs, the reset specifier is the reset number and not the module number. Reflect this in the description for the '#reset-cells' property. Reported-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
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- 10 Jun, 2024 3 commits
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Jerome Brunet authored
* v6.11/bindings: dt-bindings: clock: meson: a1: peripherals: support sys_pll input dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
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Dmitry Rokosov authored
The 'sys_pll' input is an optional clock that can be used to generate 'sys_pll_div16', which serves as one of the sources for the GEN clock. Signed-off-by:
Dmitry Rokosov <ddrokosov@salutedevices.com> Acked-by:
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Dmitry Rokosov authored
The 'syspll' PLL is a general-purpose PLL designed specifically for the CPU clock. It is capable of producing output frequencies within the range of 768MHz to 1536MHz. The 'syspll_in' source clock is an optional parent connection from the peripherals clock controller. Signed-off-by:
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