- 21 Jun, 2019 23 commits
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Rex Zhu authored
kiq can support 4 pm4 scheduler packets set_resource, map_queues, unmap_queues, query_status. Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Hawking Zhang authored
The function now will create mqd bos for both gfx queue and compute queue Signed-off-by:
Jack Xiao <jack.xiao@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Hawking Zhang authored
Similar to what we do for compute already. Signed-off-by:
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Hawking Zhang authored
currently, amdgpu will owns the first gfx queue of each pipe they are: me:0 pipe:0 queue:0 me:0 pipe:1 queue:0 Signed-off-by:
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Hawking Zhang authored
Update the structure for gfx10. Signed-off-by:
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Hawking Zhang authored
gfx10 allows to only upload me jumptable while save the whole me image at gtt memory. v2: program CP_ME_IC_BASE_CNTL to default value v3: switch to use amdgpu_bo_create_reserved to create me fw bo v4: split common code from gfx10 code Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Hawking Zhang authored
gfx10 allows to only upload ce jumptable while save the whole ce image at gtt memory. v2: program CP_CE_IC_BASE_CNTL to default value v3: switch to use amdgpu_bo_create_reserved to create ce fw bo v4: split common code from gfx10 code Signed-off-by:
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Hawking Zhang authored
gfx10 allows to only upload pfp jumptable while save the whole pfp image at gtt memory. v2: program CP_PFP_IC_BASE_CNTL to default value v3: switch to use amdgpu_bo_create_reserved to create pfp fw bo v4: split common code from gfx10 code Signed-off-by:
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Hawking Zhang authored
nbio handles bus io functionality. v1: add place holder and initial basic nbio v2.3 functions (Ray) v2: implements and expose all functions in format of nbio_v2_3_funcs (Hawking) v3: squash in updates (Alex) v4: whitespace fix (Alex) Signed-off-by:
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Leo Liu authored
For Navi10 VCN2.0, the engine supports Doorbell Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Hawking Zhang authored
Driver will get channel_number and channel_width from vram_info table, then calculate vram_width by multiply channel_number by channel_width Signed-off-by:
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Hawking Zhang authored
vram_type is saved in member vram_module[0].memory_type Signed-off-by:
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Hawking Zhang authored
A pm4 header for Navi. PM4 is the packet format used by the compute and gfx engines. Signed-off-by:
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Hawking Zhang authored
Defines the SDMA packet formats. Signed-off-by:
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Huang Rui authored
Clear state for gfx pipe. v2: squash in updates Signed-off-by:
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Huang Rui authored
Header for CP structures (MQD, etc.) V2: squash in updates Signed-off-by:
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Hawking Zhang authored
Parse the new parameters for gfx10. Signed-off-by:
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Hawking Zhang authored
two new members that specific for navi10 are included in v2_0: num_sc_per_sh and num_packer_per_sc Signed-off-by:
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Huang Rui authored
gpu info firmware stores configuration data for various IP blocks. Signed-off-by:
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Hawking Zhang authored
New gfx config parameter. Signed-off-by:
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Hawking Zhang authored
The two members are used to cache the values from gpu_info fw accordingly Signed-off-by:
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Hawking Zhang authored
For printing vram type. Signed-off-by:
Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by:
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Huang Rui authored
New vram type. Signed-off-by:
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- 20 Jun, 2019 17 commits
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Huang Rui authored
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Huang Rui authored
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Hawking Zhang authored
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Hawking Zhang authored
Update mappings for Navi10. Signed-off-by:
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Hawking Zhang authored
Updated tables for Navi10. Signed-off-by:
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Hawking Zhang authored
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Hawking Zhang authored
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Hawking Zhang authored
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Hawking Zhang authored
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Hawking Zhang authored
v2: Update regs (Alex) v3: More updates (Alex) v4: more updates (Alex) Signed-off-by:
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Hawking Zhang authored
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Hawking Zhang authored
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Hawking Zhang authored
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Hawking Zhang authored
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Hawking Zhang authored
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Hawking Zhang authored
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Hawking Zhang authored
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