- 27 Jan, 2015 4 commits
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Stephen Boyd authored
Some devices don't use mmio to interact with dividers. Split out the logic from the register read/write parts so that we can reuse the division logic elsewhere. Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Tested-by:
Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by:
Michael Turquette <mturquette@linaro.org>
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Stephen Boyd authored
Some clock drivers want to find the closest rate on the input of a mux instead of a rate that's less than or equal to the desired rate. Add a generic mux function to support this. Signed-off-by:
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Srinivas Kandagatla authored
Some of the clks can be registered & unregistered before the clk related debugfs entries are initialized at late_initcall. In the unregister path checking for only dentry before clk_debug_init() would lead dangling pointers in the debug clk list, because the list is already populated in register path and the clk pointer freed in unregister path. The side effect of not removing it from the list is either a null pointer dereference or if lucky to boot the system, the number of clk entries in debugfs disappear. We could add more checks like if (inited && !clk->dentry) but just removing the check for dentry made more sense as debugfs_remove_recursive() seems to be safe with null pointers. This will ensure that the unregistering clk would be removed from the debug list in all the code paths. Without this patch kernel would crash with log: Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = c0204000 [00000000] *pgd=00000000 Internal error: Oops: 5 [#1] SMP ARM Modules linked in: CPU: 1 PID: 1 Comm: swapper/0 Tainted: G B 3.19.0-rc3-00007-g412f9ba-dirty #840 Hardware name: Qualcomm (Flattened Device Tree) task: ed948000 ti: ed944000 task.ti: ed944000 PC is at strlen+0xc/0x40 LR is at __create_file+0x64/0x1dc pc : [<c04ee604>] lr : [<c049f1c4>] psr: 60000013 sp : ed945e40 ip : ed945e50 fp : ed945e4c r10: 00000000 r9 : c1006094 r8 : 00000000 r7 : 000041ed r6 : 00000000 r5 : ed4af998 r4 : c11b5e28 r3 : 00000000 r2 : ed945e38 r1 : a0000013 r0 : 00000000 Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c5787d Table: 8020406a DAC: 00000015 Process swapper/0 (pid: 1, stack limit = 0xed944248) Stack: (0xed945e40 to 0xed946000) 5e40: ed945e7c ed945e50 c049f1c4 c04ee604 c0fc2fa4 00000000 ecb748c0 c11c2b80 5e60: c0beec04 0000011c c0fc2fa4 00000000 ed945e94 ed945e80 c049f3e0 c049f16c 5e80: 00000000 00000000 ed945eac ed945e98 c08cbc50 c049f3c0 ecb748c0 c11c2b80 5ea0: ed945ed4 ed945eb0 c0fc3080 c08cbc30 c0beec04 c107e1d8 ecdf0600 c107e1d8 5ec0: c107e1d8 ecdf0600 ed945f54 ed945ed8 c0208ed4 c0fc2fb0 c026a784 c04ee628 5ee0: ed945f0c ed945ef0 c0f5d600 c04ee604 c0f5d5ec ef7fcc7d c0b40ecc 0000011c 5f00: ed945f54 ed945f10 c026a994 c0f5d5f8 c04ecc00 00000007 ef7fcc95 00000007 5f20: c0e90744 c0dd0884 ed945f54 c106cde0 00000007 c117f8c0 0000011c c0f5d5ec 5f40: c1006094 c100609c ed945f94 ed945f58 c0f5de34 c0208e50 00000007 00000007 5f60: c0f5d5ec be9b5ae0 00000000 c117f8c0 c0af1680 00000000 00000000 00000000 5f80: 00000000 00000000 ed945fac ed945f98 c0af169c c0f5dd2c ed944000 00000000 5fa0: 00000000 ed945fb0 c020f298 c0af168c 00000000 00000000 00000000 00000000 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 ebcc6d33 bfffca73 [<c04ee604>] (strlen) from [<c049f1c4>] (__create_file+0x64/0x1dc) [<c049f1c4>] (__create_file) from [<c049f3e0>] (debugfs_create_dir+0x2c/0x34) [<c049f3e0>] (debugfs_create_dir) from [<c08cbc50>] (clk_debug_create_one+0x2c/0x16c) [<c08cbc50>] (clk_debug_create_one) from [<c0fc3080>] (clk_debug_init+0xdc/0x144) [<c0fc3080>] (clk_debug_init) from [<c0208ed4>] (do_one_initcall+0x90/0x1e0) [<c0208ed4>] (do_one_initcall) from [<c0f5de34>] (kernel_init_freeable+0x114/0x1e0) [<c0f5de34>] (kernel_init_freeable) from [<c0af169c>] (kernel_init+0x1c/0xfc) [<c0af169c>] (kernel_init) from [<c020f298>] (ret_from_fork+0x14/0x3c) Code: c0b40ecc e1a0c00d e92dd800 e24cb004 (e5d02000) ---[ end trace b940e45b5e25c1e7 ]--- Fixes: 6314b679 "clk: Don't hold prepare_lock across debugfs creation" Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by:
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Michael Turquette authored
Merge branch 'clk-shmobile-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
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- 25 Jan, 2015 2 commits
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Michael Turquette authored
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Thierry Reding authored
This new function is similar to clk_set_parent(), except that it doesn't actually change the parent. It merely checks that the given parent clock can be a parent for the given clock. A situation where this is useful is to check that a particular setup is valid before switching to it. One specific use-case for this is atomic modesetting in the DRM framework where setting a mode is divided into a check phase where a given configuration is validated before applying changes to the hardware. Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by:
Thierry Reding <treding@nvidia.com> Reviewed-by:
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- 20 Jan, 2015 11 commits
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Oleksij Rempel authored
Provide CLK support for Alphascale ASM9260 SoC. Signed-off-by:
Oleksij Rempel <linux@rempel-privat.de> Signed-off-by:
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Peter Griffin authored
Debugging eMMC on upstream kernels it has been noticed that when the targetpack configures MMC0 clock to 200Mhz (required to switch to HS200) then everything works OK. However if the kernel sets the clock rate using clk_set_rate, then the eMMC card initialisation fails with timeouts. Lower clock speeds (the default being 50Mhz) work ok, but they we fail to get good eMMC transfer rates. Looking through the vendor kernel clock driver reveals Giuseppe had already fixed this issue, but the patch hasn't made its way upstream. The issue is fixed by changing the logic to manage the pdiv and fdiv divisors used for setting the rate inside the flexgen driver code. Pdiv is mainly targeted for low freq results, while fdiv should be used for divs =< 64. The other way can lead to 'duty cycle' issues. I have changed the original patch to keep the original behaviour in cases where the div is >64 which matches the original comment and patch description more closely. Although no clocks appear to hit this case currently when booting an upstream kernel. Signed-off-by:
Peter Griffin <peter.griffin@linaro.org> Signed-off-by:
Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by:
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Tang Yuantian authored
Freescale introduced new ARM-based socs which using the compatible clock IP block with PowerPC-based socs'. So this driver can be used on both platforms. Updated relevant descriptions and renamed this driver to better represent its meaning and keep the function of driver untouched. Signed-off-by:
Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by:
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Tang Yuantian authored
redefine variable clocks_per_pll as a struct member If there are multiple PLL clock nodes, this variable will get overwritten. Redefining it as a struct member can avoid that. Signed-off-by:
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git://linuxtv.org/snawrocki/samsungMichael Turquette authored
- Clock definitions for Exynos7 SoC peripheral devices: video scaler, USB, DMA, SPI and the audio subsystem.
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Tony Lindgren authored
The clocks on ti81xx are not compatible with omap3. On dm816x the clock source is a FAPLL (Flying Adder PLL), and on dm814x there seems to be an APLL (All Digital PLL). Let's fix up things for dm816x in preparation for adding the FAPLL support. As we already have a dummy ti81xx_dt_clk_init() in place, let's use that for now to avoid adding a dependency to the omap patches. Later on if somebody adds dm814x support we can split the ti81xx_dt_clk_init() clock init function as needed. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Tony Lindgren authored
On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL) that does not seem to be used on the other omap variants. There are four instances of the FAPLL on dm816x that each have three to seven child synthesizers. I've set up the FAPLL as a single fapll.c driver. Later on we could potentially have the PLL code generic. To do that, we would have to consider the following: 1. Setting the PLL to bypass mode also sets the child synthesizers into bypass mode. As the bypass rate can also be generated by the PLL in regular mode, there's no way for the child synthesizers to detect the bypass mode based on the parent clock rate. 2. The PLL registers control the power for each of the child syntheriser. Note that the clocks are currently still missing the set_rate implementation so things are still running based on the bootloader values. That's OK for now as most of the outputs have dividers and those can be set using the existing TI component clock code. I have verified that the extclk rates are correct for a few clocks, so adding the set_rate support should be fairly trivial later on. This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02 patches published at: http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by:
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Stephen Boyd authored
We don't need to fetch the parent index for clocks if they only have one parent. Doing this also avoid an unnecessary allocation for the parent cache. Signed-off-by:
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Sergei Shtylyov authored
In case CLK_GATE_HIWORD_MASK flag is passed to clk_register_gate(), the bit # should be no higher than 15, however the corresponding check is obviously off- by-one. Fixes: 04577994 ("clk: gate: add CLK_GATE_HIWORD_MASK") Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Kevin Hao authored
In order to fix the following section mismatch warning: WARNING: drivers/clk/built-in.o(.data+0xe4): Section mismatch in reference from the variable ppc_corenet_clk_driver to the function .init.text:ppc_corenet_clk_probe() The variable ppc_corenet_clk_driver references the function __init ppc_corenet_clk_probe() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/built-in.o(.data+0x10c): Section mismatch in reference from the variable ppc_corenet_clk_driver to the variable .init.rodata:ppc_clk_ids The variable ppc_corenet_clk_driver references the variable __initconst ppc_clk_ids If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console We can't just add the __init annotation to ppc_corenet_clk_driver or remove the __init from ppc_corenet_clk_probe() and ppc_clk_ids. So choose to use CLK_OF_DECLARE to scan and init the clock devices. Signed-off-by:
Kevin Hao <haokexin@gmail.com> Acked-by:
Scott Wood <scottwood@freescale.com> Acked-by:
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Kevin Hao authored
So the boards which has COMMON_CLK enabled don't have to invoke this in its board specific file. Signed-off-by:
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- 17 Jan, 2015 6 commits
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Krzysztof Kozlowski authored
The memory allocated by basic clock divider/gate/mux (struct clk_gate, clk_divider and clk_mux) was leaking. During driver unbind or probe failure the driver only unregistered the clocks. Use clk_unregister_{gate,divider,mux} to release all resources. Signed-off-by:Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by:
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Krzysztof Kozlowski authored
The common clk_register_{divider,gate,mux} functions allocated memory for internal data which wasn't freed anywhere. Drivers using these helpers could only unregister clocks but the memory would still leak. Add corresponding unregister functions which will release all resources. Signed-off-by: -
Max Filippov authored
The driver allows using CDCE706 in its default configuration recorded in EEPROM and adjusting of synthesized clocks by consumers. Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com> Signed-off-by:
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Stanimir Varbanov authored
The commit 646cafc6 (clk: Change clk_ops->determine_rate to return a clk_hw as the best parent) opens a possibility for null pointer dereference, fix this. Signed-off-by:
Stanimir Varbanov <svarbanov@mm-sol.com> Reviewed-by:
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Kevin Hao authored
This reverts commit da788acb. That commit tried to fix the section mismatch warning by moving the ppc_corenet_clk_driver struct to init section. This is definitely wrong because the kernel would free the memories occupied by this struct after boot while this driver is still registered in the driver core. The kernel would panic when accessing this driver struct. Cc: stable@vger.kernel.org # 3.17 Signed-off-by:
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Heiko Stübner authored
Lockdep reported a possible deadlock between the cpuclk lock and for example the i2c driver. CPU0 CPU1 ---- ---- lock(clk_lock); local_irq_disable(); lock(&(&i2c->lock)->rlock); lock(clk_lock); <Interrupt> lock(&(&i2c->lock)->rlock); *** DEADLOCK *** The generic clock-types of the core ccf already use spin_lock_irqsave when touching clock registers, so do the same for the cpuclk. Signed-off-by:Heiko Stuebner <heiko@sntech.de> Reviewed-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
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- 15 Jan, 2015 3 commits
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Padmavathi Venna authored
Add required clk support for I2S, PCM and SPDIF. Signed-off-by:
Padmavathi Venna <padma.v@samsung.com> Reviewed-by:
Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
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Padmavathi Venna authored
Add clock support for 5 SPI channels. Signed-off-by:
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Padmavathi Venna authored
Add support for PDMA0 and PDMA1 gate clks. Signed-off-by:
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- 13 Jan, 2015 2 commits
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Jisheng Zhang authored
The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable register is for nfc. Current code use bit19 for non-exist "smemc" incorrectly, this prevents eMMC from working due to the sdhci's "core" clk is still gated. Signed-off-by:
Jisheng Zhang <jszhang@marvell.com> Cc: stable@vger.kernel.org # 3.16+ Signed-off-by:
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Boris Brezillon authored
All slow clk users are not properly claiming it (get + prepare + enable) before using it. If all users properly claiming this clock release it, the clock is disabled, but faulty users still depends on it, and the system hangs. This fix prevents the slow clock from being disabled, and should solve the hanging issue, but offending drivers should be patched to properly claim this clock. Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Reported-by:
Bo Shen <voice.shen@atmel.com> Cc: stable@vger.kernel.org Signed-off-by:
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- 12 Jan, 2015 1 commit
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Michael Turquette authored
Merge tag 'v3.19-rockhip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes - two currently unused clocks that need to stay enabled - fix the lock bit locations of the rk3066 plls - fix rk3288 core divider values to the ones actually specified by the soc vendor
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- 08 Jan, 2015 7 commits
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Sergei Shtylyov authored
Add the ADSP clock support to the R-Car generation 2 CPG driver. This clock gets derived from PLL1. The layout of the ADSPCKCR register is similar to those of the clocks supported by the 'clk-div6' driver but the divider encoding is non-linear, so can't be supported by that driver... Based on the original patch by Konstantin Kozhevnikov <konstantin.kozhevnikov@cogentembedded.com>. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Sergei Shtylyov authored
Add the RCAN clock support to the R-Car generation 2 CPG driver. This clock gets derived from the USB_EXTAL clock, dividing it by 6. The layout of the RCANCKCR register is similar to those of the clocks supported by the 'clk-div6' driver but has no divider field, and so can't be supported by that driver... Signed-off-by:
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Ulrich Hecht authored
Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Ulrich Hecht authored
Driver for the R8A73A4's clocks that are too specific to be supported by a generic driver. Signed-off-by:
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Yoshihiro Kaneko authored
Signed-off-by:
Yoshihiro Kaneko <ykaneko0929@gmail.com> Acked-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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Hisashi Nakamura authored
R-Car M2N (r8a7793) clock is handled in R-Car Gen2 clock driver. Signed-off-by:
Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by:
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Geert Uytterhoeven authored
While DIV6 clocks require the divisor field to be non-zero when stopping the clock, some clocks (e.g. ZB on sh73a0) fail to be re-enabled later if the divisor field is changed when stopping the clock. The reason for this is unknown. To fix this, do not touch the divisor field if it's already non-zero. On kzm9g, the smsc911x Ethernet controller is connected to the sh73a0 Bus State Controller, which is clocked by the ZB clock. Without this fix, if the ZB clock is disabled during system suspend, and re-enabled during resume, the kernel locks up when the smsc911x driver tries to access the Ethernet registers. Signed-off-by:
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- 28 Dec, 2014 2 commits
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Heiko Stuebner authored
Commit 0e5bdb3f (clk: rockchip: switch to using the new cpuclk type for armclk) didn't take into account that the divider used on rk3288 are of the (n+1) type. The rk3066 and rk3188 socs use more complex divider types making it necessary for the list-elements to be the real register-values to write. Therefore reduce divider values in the table accordingly so that they really are the values that should be written to the registers and match the dividers actually specified for the rk3288. Reported-by:
Sonny Rao <sonnyrao@chromium.org> Fixes: 0e5bdb3f ("clk: rockchip: switch to using the new cpuclk type for armclk") Signed-off-by:
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Heiko Stuebner authored
The bit locations indicating the locking status of the plls on rk3066 are shifted by one to the right when compared to the rk3188, bits [7:4] instead of [8:5] on the rk3188, thus indicating the locking state of the wrong pll or a completely different information in case of the gpll. The recently introduced pll init code exposed that problem on some rk3066 boards when it tried to bring the boot-pll value in line with the value from the rate table. Fix this by defining separate pll definitions for rk3066 with the correct locking indices. Signed-off-by:
FUKAUMI Naoki <naobsd@gmail.com> Cc: stable@vger.kernel.org
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- 23 Dec, 2014 2 commits
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Vivek Gautam authored
Adding required gate clocks for USB3.0 DRD controller present on Exynos7. Signed-off-by:
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Tony K Nadackal authored
Add clock support for the MSCL block for Exynos7. Signed-off-by:
Tony K Nadackal <tony.kn@samsung.com> Reviewed-by:
Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by:
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