- 14 Oct, 2020 11 commits
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Alex Deucher authored
Fix this to avoid build problems if DRM_AMD_DC_DCN3_02 is defined, but DRM_AMD_DC_DCN3_01 is not. Fixes: 36d26912 ("drm/amd/display: Add support for DCN302 (v2)") Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Acked-by:
Randy Dunlap <rdunlap@infradead.org> Reported-by:
Alex Deucher <alexander.deucher@amd.com>
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Kent Russell authored
Now that we use kvmalloc for the crat_image, we need to use kvfree when we destroy this. Fixes: d0e63b34 ("drm/amdkfd: Use kvmalloc instead of kmalloc for VCRAT") Reported-by:
Morris Zhang <shiwu.zhang@amd.clm> Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Veerabadhran G authored
Synchronize the ring usage for vcn1 and jpeg1 to workaround a hardware bug. Signed-off-by:
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Hawking Zhang authored
add mp0 11_0_12 for dimgrey_cavefish to the mem training supported list, otherwise the modeprobe would fail on dimgrey_cavefish with latest vbios. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Huang Rui authored
The driver needn't load smu binary on APU platforms. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Madhav Chauhan <madhav.chauhan@amd.com> Signed-off-by:
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Evan Quan authored
To avoid underflow seen on Polaris10 with some 3440x1440 144Hz displays. As the threshold of 190 us cuts too close to minVBlankTime of 192 us. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Mauro Carvalho Chehab authored
As reported by Sphinx: Documentation/gpu/amdgpu.rst:200: WARNING: Inline emphasis start-string without end-string. Signed-off-by:
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by:
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Mauro Carvalho Chehab authored
As warned when running "make htmldocs": ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:345: warning: Function parameter or member 'force_timing_sync' not described in 'amdgpu_display_manager' This new struct member was not documented at kernel-doc markup. Fixes: 3d4e52d0 ("drm/amd/display: Add debugfs for forcing stream timing sync") Signed-off-by:
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Bernard Zhao authored
Functions (disable_all_writeback_pipes_for_stream & dc_enable_stereo & dc_post_update_surfaces_to_stream) always return true, there is no need to keep the return value. This change is to make the code a bit more readable. Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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kernel test robot authored
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:608:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: b4a7db71 ("drm/amdgpu: add per device user friendly xgmi events for vega20") CC: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Alex Deucher authored
GPU reset might get called during init time, before sw_init has been called. Reviewed-by:
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- 12 Oct, 2020 29 commits
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Roman Li authored
Display Manager support for green_sardine Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Roman Li authored
Display Core support for green_sardine Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Tao Zhou authored
Add DM block support for dimgrey_cavefish. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Jack Gui <Jack.Gui@amd.com> Signed-off-by:
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Tao Zhou authored
dimgrey_cavefish has no ASD ucode currently, remove its initialization. Signed-off-by:
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Bhawanpreet Lakha authored
Handle CAVE_DIMGREY_CAVEFISH in amdgpu_dm v2: fix rebase typo (Alex) Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
- add DCN302 resource, irq service, dmub loader, - handle DC_VERSION_DCN_3_02 - define DCN302 power gating functions - handle DCN302 in GPIO files - define I2C regs - add CONFIG_DRM_AMD_DC_DCN3_02 guard v2: rebase fixes (Alex) Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Signed-off-by:
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Tao Zhou authored
Per PMFW 59.7.0. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by:
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Tao Zhou authored
Remove gpu_info fw support for dimgrey_cavefish, gpu info can be got from ip discovery. Signed-off-by:
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Tao Zhou authored
Set ih CG flag for dimgrey_cavefish. Signed-off-by:
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Tao Zhou authored
Set hdp CG and LS flag for dimgrey_cavefish. Signed-off-by:
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Tao Zhou authored
Add psp and smu block for dimgrey_cavefish with psp firmware load type. Signed-off-by:
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Tao Zhou authored
Per PMFW 59.5.0. v2: refine subject and commit message, fix typo Signed-off-by:
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Tao Zhou authored
Update driver if version from 0x5 to 0x6 for dimgrey_cavefish, per PMFW 59.04.0. Signed-off-by:
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James Zhu authored
Enable jpeg3.0 ip block for dimgrey_cavefish. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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James Zhu authored
Enable vcn3.0 ip block for dimgrey_cavefish. Signed-off-by:
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Tao Zhou authored
Update driver if version from 0x4 to 0x5 for dimgrey_cavefish, per PMFW 59.02.0. Signed-off-by:
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Tao Zhou authored
Set athub/mmhub PG flag for dimgrey_cavefish. Signed-off-by:
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Tao Zhou authored
Set mc CG and LS flag for dimgrey_cavefish. Signed-off-by:
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Tao Zhou authored
Enable GFX MGCG, CGCG and 3DCG for dimgrey_cavefish. Signed-off-by:
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Tao Zhou authored
Update driver if version according to PMFW with version 0x003B0100. Signed-off-by:
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Tao Zhou authored
Same as navy_flounder, the athub ip of dimgrey_cavefish is v2.1. Signed-off-by:
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Tao Zhou authored
Support both back and front door loading for dimgrey_cavefish. Signed-off-by:
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James Zhu authored
Enable JPEG3.0 PG and CG for dimgrey_cavefish. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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James Zhu authored
Enable VCN3.0 PG and CG for dimgrey_cavefish Signed-off-by:
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Chengming Gui authored
Add KFD support. Signed-off-by:
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Chengming Gui authored
Add KFD support for dimgrey cavefish. v2: rebase (Alex) Signed-off-by:
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Tao Zhou authored
Add gc golden setting for dimgrey_cavefish. Signed-off-by:
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Tao Zhou authored
Same as sienna_cichlid, dimgrey_cavefish supports WAIT_REG_MEM packet. Signed-off-by:
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Tao Zhou authored
Add check before reroute ih setting, it's not supported by some ASICs. Signed-off-by:
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