- 25 Mar, 2014 8 commits
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Gabriel FERNANDEZ authored
Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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Gabriel FERNANDEZ authored
The patch supports the A9-mux clocks used by ClockGenA9 A9-mux clock : Multiplexer inside ClockGenA9. A9 clock can be driven by either PLL or External clock (with an optional divide-by-2). This is implemented as 3-parent clock : PLL, Ext-clk OR Ext-clk/2 Signed-off-by:
Pankaj Dev <pankaj.dev@st.com> Signed-off-by:
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Gabriel FERNANDEZ authored
The patch added support for DT registration of ClockGenA9/DDR/GPU ClockgenA9/DDR : It includes c32 type PLL (also in ClockgenA1x), hence only CLK_OF_DECLARE implementation is required. ClockgenGPU : It includes c65 type PLL (also in ClockgenAx), hence only CLK_OF_DECLARE implementation is required. Signed-off-by:
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Gabriel FERNANDEZ authored
The patch supports the 216/432/660 type Quad Frequency Synthesizers used by ClockGenB/C/D/E/F QUADFS clock : It includes support for all 216/432/660 type Quad Frequency Synthesizers : implemented as Fixed Parent / Rate / Gate clock, with clock rate calculated reading H/w settings done at BOOT. QuadFS have 4 outputs : chan0 chan1 chan2 chan3 Signed-off-by:
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Gabriel FERNANDEZ authored
The patch supports the VCC-mux and MUX clocks used by ClockGenC/F VCC-mux clock : Divider-Multiplexer-Gate inside ClockGenC/F It includes support for each channel : 4-parent Multiplexer, Post Divide by 1, 2, 4 or 8, Gate to switch OFF the output channel. The clock is implemented using generic clocks implemented in the kernel clk_divider, clk_mux, clk_gate and clk_composite (to combine all) MUX clock : 2-parent clock used inside ClockGenC/F. The clock is implemented using generic clocks implemented in the kernel clk_mux. Signed-off-by:
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Gabriel FERNANDEZ authored
The patch supports the c65/c32 type PLLs used by ClockGenA(s) PLL clock : It includes support for all c65/c32 type PLLs inside ClockGenA(s) : implemented as Fixed Parent / Fixed Rate clock, with clock rate calculated reading H/w settings done at BOOT. c65 PLLs have 2 outputs : HS and LS c32 PLLs have 1-4 outputs : ODFx Signed-off-by:
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Gabriel FERNANDEZ authored
The patch supports the DIVMUX and PreDiv clocks used by ClockGenA(s) DIVMUX clock : Divider-Multiplexer-Gate inside ClockGenA(s) It includes support for each channel : 3-parent Multiplexer, Divider for each Parent, Gate to switch OFF the output channel. The clock is implemented using generic clocks implemented in the kernel clk_divider and clk_mux. PreDiv clock : Fixed Divider Clock used inside ClockGenA(s) to divide the oscillator clock by factor-of-16. The clock is implemented using generic clocks implemented in the kernel clk_divider. Signed-off-by:
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Alex Elder authored
Add a new clk_ops->debug_init method to allow a clock hardware driver to populate the clock's debugfs directory with entries beyond those common for every clock. Signed-off-by:
Alex Elder <elder@linaro.org> Signed-off-by:
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- 24 Mar, 2014 2 commits
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Krzysztof Kozlowski authored
of_find_node_by_name() walks over all nodes and can thus walk outside of the parent node. Use of_get_child_by_name() instead. Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
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Krzysztof Kozlowski authored
If parent device does not have of_node set the s2mps11_clk_parse_dt() returned NULL. This NULL was later passed to of_clk_add_provider() which dereferenced it in pr_debug() call. Signed-off-by:
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- 21 Mar, 2014 2 commits
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Zhangfei Gao authored
drivers/clk/hisilicon/clk-hi3620.c:338 mmc_clk_delay() warn: always true condition '(para >= 0) => (0-u32max >= 0)' Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by:
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Wolfram Sang authored
Signed-off-by:
Wolfram Sang <wsa@sang-engineering.com> Signed-off-by:
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- 20 Mar, 2014 4 commits
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Sascha Hauer authored
If a rate change failed it's the opportunity of the caller to handle this. Do not spam the log with a message. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
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Mike Turquette authored
Framework is not ARM specific and used by many architectures. Change ML from LAKML to LKML. Signed-off-by: -
Gregory CLEMENT authored
Until now the clock providers were initialized in the order found in the device tree. This led to have the dependencies between the clocks not respected: children clocks could be initialized before their parent clocks. Instead of forcing each platform to manage its own initialization order, this patch adds this work inside the framework itself. Using the data of the device tree the of_clk_init function now delayed the initialization of a clock provider if its parent provider was not ready yet. The strict dependency check (all parents of a given clk must be initialized) was added by Boris BREZILLON Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by:
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Tang Yuantian authored
The clock bindings for Freescale CoreNet platform are updated. So, the driver needs to be updated accordingly. The main changes include: - Added a new node to present the input system clock - Changed PLL and MUX's compatible string Signed-off-by:
Tang Yuantian <Yuantian.Tang@freescale.com> Acked-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
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- 19 Mar, 2014 18 commits
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Jean-Jacques Hiblot authored
Signed-off-by:
Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by:
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Jean-Jacques Hiblot authored
The PCKRDY bit is not set until the system clock is enabled. This patch moves the management of the ready status in the system clock driver. Signed-off-by:
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Boris BREZILLON authored
System clks are just gates, and thus do not provide any rate operations. Authorize clk rate change to be propagated to system clk parents. Signed-off-by:
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Boris BREZILLON authored
Implement the determine_rate callback to choose the best parent clk that fulfills the requested rate. Signed-off-by:
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Laurent Pinchart authored
Briefly document the common clock framework locking scheme from a clock driver point of view. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Mike Turquette authored
Merge tag 'clk-hisi' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilcon updating clock drivers for Hisilicon
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Emilio López authored
This should read MOD0 and not MMC; MMC is just one example of a MOD0 clock. Signed-off-by:
Emilio López <emilio@elopez.com.ar> Signed-off-by:
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Emilio López authored
Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro. Reported-by:
Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by:
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Emilio López authored
Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i. Signed-off-by:
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https://bitbucket.org/emiliolopez/linuxMike Turquette authored
Allwinner sunXi SoCs clock changes This adds support for the new, more correct clock node naming and gets the A10 compatibles in line with the rest of the other SoCs. It also adds support for the USB, GMAC and A31's PLL6 clocks. Some of these changes also require DT modifications that will be merged via arm-soc.
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Haojian Zhuang authored
Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by:Haojian Zhuang <haojian.zhuang@linaro.org>
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Haojian Zhuang authored
Now only fixed rate clocks are appended into the clock driver. Signed-off-by: -
Haojian Zhuang authored
The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: -
Dinh Nguyen authored
WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_pll_init() The variable socfpga_child_clocks references the function __init socfpga_pll_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_periph_init() The variable socfpga_child_clocks references the function __init socfpga_periph_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_gate_init() The variable socfpga_child_clocks references the function __init socfpga_gate_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Reported-by:
Dinh Nguyen <dinguyen@altera.com> Signed-off-by:
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git://git.infradead.org/linux-mvebuMike Turquette authored
clock: mvebu new SoC changes for v3.15 (incremental pull #2) - mvebu (Armada 375) - fix ratio register offest - mvebu (Armada 380) - expand core divider clock driver to support 380 SoC (enables nand support) -
Tushar Behera authored
Since clock operation within S2MPS11 and S5M8767 are similar, we can support both the devices within a single driver. Signed-off-by:
Tushar Behera <tushar.behera@linaro.org> Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Reviewed-by:
Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by:
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Tushar Behera authored
The clocks in S2MPS11 and S5M8767 are managed in the same way, baring a difference in the register offset. It would be better to update existing S2MPS11 driver to support the clocks in S5M8767, rather than creating an almost duplicate driver altogether. Signed-off-by:
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Jonas Jensen authored
MOXA ART SoCs allow to determine PLL output and APB frequencies by reading registers holding multiplier and divisor information. Add a clock driver for this SoC. Signed-off-by:
Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by:
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- 13 Mar, 2014 3 commits
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Ezequiel Garcia authored
The Core Divider clock support two new compatible strings for Armada 375 and Armada 380 SoCs. Add the compatible strings to the documentation. Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-7-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by:
Jason Cooper <jason@lakedaemon.net>
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Ezequiel Garcia authored
This commit adds support for the Core Divider clocks of the Armada 380 SoCs. Similarly to Armada 370 and XP, the Core Divider clocks of the 380 have gate capabilities. The only difference is the register layout. Signed-off-by:
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Ezequiel Garcia authored
This commit fixes the ratio register offset which is 0x4, as per the Armada 375 SoC specification. Signed-off-by:
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- 27 Feb, 2014 3 commits
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Mike Turquette authored
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Tomi Valkeinen authored
ti/clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the ti/clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by:
Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by:
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Tomi Valkeinen authored
clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by:
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