- 24 May, 2024 2 commits
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPCNTR register macro. Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d9434a718658d7dc6dba1e8a54f80cd1503d0b33.1716469091.git.jani.nikula@intel.comSigned-off-by:
Jani Nikula <jani.nikula@intel.com>
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPADDR_VLV register macro. Reviewed-by:
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- 23 May, 2024 2 commits
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José Roberto de Souza authored
Process name help us track what application caused the gpug hang, this is crucial when running several applications at the same time. v2: - handle Xe KMD exec_queues without VM v3: - use get_pid_task() (suggested by Nirmoy) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by:
Nirmoy Das <nirmoy.das@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240522201203.145403-1-jose.souza@intel.com
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Ville Syrjälä authored
Instead of that huge _PICK() let's use PICK_EVEN_2RANGES() for the SEL_FETCH_PLANE registers. A bit more tedious to have to define 8 raw register offsets for everything, but perhaps a bit easier to understand since we use a standard mechanism now instead of hand rolling the arithmetic. Also bloat-o-meter says: add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-326 (-326) Function old new delta icl_plane_update_arm 510 446 -64 icl_plane_disable_sel_fetch_arm.isra 158 54 -104 icl_plane_update_noarm 1898 1740 -158 Total: Before=2574502, After=2574176, chg -0.01% v2: s/mtl+/tgl+/ comments to reflect actual reality Signed-off-by:
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- 22 May, 2024 19 commits
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Ville Syrjälä authored
Note which sprite registers are valid for which platforms. Signed-off-by:
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Ville Syrjälä authored
Group the sprite plane register definitions such that everything to do with the same register is in one place. Signed-off-by:
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Ville Syrjälä authored
Add some notes indicating which plane registers/bits are valid for which platforms. Signed-off-by:
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Ville Syrjälä authored
Group the pre-skl primary plane register definitions sensible, and toss in a few comments to indicate which platforms have what. Signed-off-by:
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Ville Syrjälä authored
Relocate all pre-skl primary plane register definitions into their own declutter i915_reg.h. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by:
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Ville Syrjälä authored
PIPEGCMAX was left behind when all other gamma registers moved into intel_color_regs.h. Signed-off-by:
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Ville Syrjälä authored
Make a more thorough split between universal planes vs. cursors by defining the contents of the cursor WM/DDB registers separately. Signed-off-by:
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Ville Syrjälä authored
Rename the selective fetch plane registers to match the spec. Signed-off-by:
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Ville Syrjälä authored
PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000 range. so using _MMIO_TRANS2() for it is not really correct. Also since this is a pipe register, and not present on CHV, the registers will be equally spaced out, so we can use the simpler _MMIO_PIPE() instead of _MMIO_PIPE2(). Signed-off-by:
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Ville Syrjälä authored
Split the cursor stuff from the rest of the selective fetch plane registers so that we can collect all cursor registers in intel_cursor_regs.h. Also take the opportunity to rename the registers to match the spec. v2: Pass the correct register offset fpr pipe B (Jani) s/mtl+/tgl+/ as that's where this was introduced Drop the bogus SEL_FETCH_CUR_CTL_ENABLE bit, the contents actually match the normal CUR_CTL register Reviewed-by: -
Ville Syrjälä authored
Group the cursor register defines such that everything to do with one register is in one place. Also, while we are touching these protect all the macro arguments for good measure. Signed-off-by:
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Ville Syrjälä authored
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch of unnecessary head scratching. Add aliases using the skl+ plane names. And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1 as we only ever have 0-2 sprites per pipe on those platforms. v2: Don't break icl_nv12_y_plane_mask() (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Vidya Srinivas authored
In some scenarios, the DPT object gets shrunk but the actual framebuffer did not and thus its still there on the DPT's vm->bound_list. Then it tries to rewrite the PTEs via a stale CPU mapping. This causes panic. Cc: stable@vger.kernel.org Reported-by:
Shawn Lee <shawn.c.lee@intel.com> Fixes: 0dc987b6 ("drm/i915/display: Add smem fallback allocation for dpt") Signed-off-by:
Vidya Srinivas <vidya.srinivas@intel.com> [vsyrjala: Add TODO comment] Signed-off-by:
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Ville Syrjälä authored
Bspec lists the mas TMDS bitrate as 6 Gbps on ADL-S/ADL-P/DG2. Bump our limit to match. v2: Bump for ADL-S as well (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Gustavo Sousa authored
Load Battlemage's DMC. We re-use XELPDP_DMC_MAX_FW_SIZE since BMG's display is a derivative of Xe_LPD+ and has the same MMIO offset limits. Reviewed-by:
Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510140532.112352-2-gustavo.sousa@intel.comSigned-off-by:
Gustavo Sousa <gustavo.sousa@intel.com>
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Suraj Kandpal authored
Check mst_port field in intel_connector to check connector type rather than rely on encoder as it may not be attached to connector at times. --v2 -Add closes tag [Imre] Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10898Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240521081458.1500327-3-suraj.kandpal@intel.com
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Suraj Kandpal authored
Move assignment of aux after connector type check as port may not exist if connector is not DPMST. --v2 -Fix unwanted change in intel_encoder check [Jani] Signed-off-by:
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Jani Nikula authored
Now that the PCI ID macros allow us to pass in the macro to use, stop redefining INTEL_VGA_DEVICE. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240515165651.1230465-2-jani.nikula@intel.comSigned-off-by:
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Jani Nikula authored
The PCI ID macros in xe_pciids.h allow passing in the macro to operate on each PCI ID, making it more flexible. Convert i915_pciids.h to the same pattern. INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and unconditionally uses INTEL_QUANTA_VGA_DEVICE(). Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
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- 21 May, 2024 1 commit
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Ryszard Knop authored
The drm-intel repo is moving from the classic fd.o git host to GitLab. Update its location with a URL matching other fd.o GitLab kernel trees. Signed-off-by:
Ryszard Knop <ryszard.knop@intel.com> Acked-by:
Tvrtko Ursulin <tursulin@ursulin.net> Acked-by:
Lucas De Marchi <lucas.demarchi@intel.com> Acked-by:
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- 20 May, 2024 3 commits
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Jouni Högander authored
PSR2_CTL[Block Count Number] is not used by LunarLake do not configure it. Bspec: 69885 Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-4-jouni.hogander@intel.com
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Jouni Högander authored
On LunarLake PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this into account when enabling PSR2_CTL. Bspec: 69885 Signed-off-by:
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Jouni Högander authored
On LunarLake maximum for IO and Fast Wake time line counts are 68: 6 bits + 5 lines added by the HW. Take this into account in calculation and when writing the IO Wake lines. v2: maximum line count is 68 (6 bits + 5 lines added by HW) Signed-off-by:
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- 17 May, 2024 1 commit
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Nirmoy Das authored
Commit 8d4ba9fc ("drm/i915/selftests: Pick correct caching mode.") was not complete as for non LLC sharing platforms cpu read can happen from LLC which probably doesn't have the latest changes made by GPU. Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com> Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> Fixes: 8d4ba9fc ("drm/i915/selftests: Pick correct caching mode.") Reviewed-by:
Jonathan Cavitt <jonathan.cavitt@intel.com> Reviewed-by:
Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240516151403.2875-1-nirmoy.das@intel.comSigned-off-by:
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- 16 May, 2024 8 commits
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURSURFLIVE register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CUR_CHICKEN register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CUR_FBC_CTL register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURSIZE register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURPOS_ERLY_TPT register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURPOS register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURBASE register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURCNTR register macro. Reviewed-by:
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- 15 May, 2024 4 commits
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Jani Nikula authored
It's confusing for INTEL_RPLP_IDS() to include INTEL_RPLU_IDS(). Even if we treat them the same elsewhere, the lists of PCI IDs should not. Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Reviewed-by:
Bjorn Helgaas <bhelgaas@google.com> Link: https://patchwork.freedesktop.org/patch/msgid/28fe0910efb93a28c400728af14beff015667f42.1715340032.git.jani.nikula@intel.comSigned-off-by:
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Jani Nikula authored
Most other PCI ID macros do not encode the gen in the name. Follow suit for TGL. Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Reviewed-by:
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Jani Nikula authored
Most other PCI ID macros do not encode the gen in the name. Follow suit for ICL. Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Reviewed-by:
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Jani Nikula authored
It's confusing for INTEL_CFL_IDS() to include all WHL and CML PCI IDs. Even if we treat them the same in a lot of places, CML is a platform of its own, and the lists of PCI IDs should not conflate them. Largely go by the idea that if a platform has a name, group its PCI IDs together. That said, AML is special, having both KBL and CFL variants. Leave that alone. v2: Also split out WHL not just CML (Rodrigo) Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Reviewed-by:
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