- 10 Dec, 2015 7 commits
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Wayne Boyer authored
Do some further clean up based on the initial review of drm/i915: Separate cherryview from valleyview. In this case remove a hack for VLV A0. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Wayne Boyer <wayne.boyer@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1449514270-15171-4-git-send-email-wayne.boyer@intel.comReviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com>
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Wayne Boyer authored
Do some further clean up based on the initial review of drm/i915: Separate cherryview from valleyview. In this case check for '(GEN7 || GEN8) && HAS_PCH_SPLIT' since we're reading FUSE_STRAP and SFUSE_STRAP which live in the PCH. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Wayne Boyer authored
The cherryview device shares many characteristics with the valleyview device. When support was added to the driver for cherryview, the corresponding device info structure included .is_valleyview = 1. This is not correct and leads to some confusion. This patch changes .is_valleyview to .is_cherryview in the cherryview device info structure and simplifies the IS_CHERRYVIEW macro. Then where appropriate, instances of IS_VALLEYVIEW are replaced with IS_VALLEYVIEW || IS_CHERRYVIEW or equivalent. v2: Use IS_VALLEYVIEW || IS_CHERRYVIEW instead of defining a new macro. Also add followup patches to fix issues discovered during the first review. (Ville) v3: Fix some style issues and one gen check. Remove CRT related changes as CRT is not supported on CHV. (Imre, Ville) v4: Make a few more optimizations. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:Jani Nikula <jani.nikula@intel.com>
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Joonas Lahtinen authored
In order to avoid accessing GPU registers while GPU is suspended cancel the hangcheck work before calling intel_suspend_complete which actually puts the GPU to suspend. Otherwise hangcheck might do MMIO reads to a suspended GPU. Placement before intel_guc_suspend is imitated from i915_drm_suspend which cancels the work at i915_gem_suspend, to keep the functions similar. On VLV systems, namely BYT, this was causing an error during runtime suspend cycle: [drm:vlv_check_no_gt_access [i915]] *ERROR* GT register access while GT waking disabled Testcase: igt/pm_rpm/basic-rte Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93121Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1449669373-8588-1-git-send-email-joonas.lahtinen@linux.intel.comReviewed-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Libin Yang authored
This patch adds support for DP MST audio in i915. Enable audio codec when DP MST is enabled if has_audio flag is set. Disable audio codec when DP MST is disabled if has_audio flag is set. Another separated patches to support DP MST audio will be implemented in audio driver. Reviewed-by:
Ander Conselvan de Oliveira <conselvan2@gmail.com> Signed-off-by:
Libin Yang <libin.yang@linux.intel.com> Signed-off-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
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Libin Yang authored
This adds code to initialise the SDP streams for a sink in the simplest ordering. I've no idea how you'd want to control the ordering at this level, so don't bother until someone comes up with a use case. Reviewed-by:
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Dave Gordon authored
All of these iterator macros require a 'temp' argument, used merely to hold internal partial results. We can instead declare the temporary variable inside the macro, so the caller need not provide it. Some of the old code contained nested iterators that actually reused the same 'temp' variable for both inner and outer instances. It's quite surprising that this didn't introduce bugs! But it does show that the value of 'temp' isn't required to persist during the iterated body. Signed-off-by:
Dave Gordon <david.s.gordon@intel.com> Signed-off-by:
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- 09 Dec, 2015 6 commits
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Rodrigo Vivi authored
Kabylake A0 is based on Skylake H0. v2: Don't assume revid+7 and only load the one we are sure about. v3: Rebase on top of latest changes. v4: Accept cleaner solution from Jani with kbl_stepping_info starting on H0 instead of put a hack on revid. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
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Sudip Mukherjee authored
We were not checking the return value of drm_encoder_init() which can fail. And if it fails then we will be working with an uninitialized encoder. Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by:
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Chris Wilson authored
Userspace can pass in an offset that it presumes the object is located at. The kernel will then do its utmost to fit the object into that location. The assumption is that userspace is handling its own object locations (for example along with full-ppgtt) and that the kernel will rarely have to make space for the user's requests. Signed-off-by:
Michel Thierry <michel.thierry@intel.com> Acked-by: PDT Signed-off-by:
Thomas Daniel <thomas.daniel@intel.com> Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449575707-20933-1-git-send-email-thomas.daniel@intel.com
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Julia Lawall authored
The intel_dvo_dev_ops structures are never modified, so declare them as const. Done with the help of Coccinelle. Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Rodrigo Vivi authored
GuC has no version for KBL published yet and it is not recommended to load the Skylake one, so let's avoid loading this for now while we don't have the proper GuC firmware for Kabylake. Signed-off-by:
Alex Dai <yu.dai@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449622718-21684-1-git-send-email-rodrigo.vivi@intel.com
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Rodrigo Vivi authored
Let's introduce ULT and ULX Kabylake definitions and start using it for a propper DDI buffer translation. v2: Remove extra white space. (Paulo) Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com>
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- 08 Dec, 2015 9 commits
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Imre Deak authored
As described in the code comment, I couldn't set the minimum RPS frequency on my BYT-M B0 to the minimum allowed as reported by Punit. Fix this by clamping the minimum value to the first one that was accepted on my machine. Atm this issue doesn't cause any test failures, since in igt/pm_rps we only check the cached version of the current frequency which is the same what has been set. In the future we'll add checks for the actual frequency too, and for that to pass this fix is necessary. Signed-off-by:
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Ville Syrjälä authored
Currently we disable some parts of FDI setup after a failed link training. But despite that we continue with the modeset as if everything is fine. This results in tons of noise from the state checker, and it means we're not following the proper modeset sequence for the rest of crtc enabling, nor for crtc disabling. Ideally we should abort the modeset and follow the proper disable sequence to shut off everything we enabled so far, but that would require a big rework of the modeset code. So instead just leave FDI up and running in its untrained state, and log an error. This is what we do on older platforms too. v2: Fix a typo in the commit message Signed-off-by:
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Ville Syrjälä authored
Currently we leave the LPT-H VGA dotclock running after turning the pipe/fdi/port/etc. Properly disable the VGA dotclock as specified in the modeset sequence. v2: Fix commit message typo (Paulo) Signed-off-by:
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Ville Syrjälä authored
Extract the LPT-H VGA dotclock disable to a separate function in anticipation of further use. While at it move the sb_lock locking inwards when enabling the VGA dotclock, as it's only needed to protect the sideband accesses. v2: Keep the PIXCLK_GATE_GATE name for 0 (Paulo) Signed-off-by:
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Ville Syrjälä authored
Bspec modeset sequence tells us to disable the PCH transcoder and FDI after the CRT port on LPT-H, so let's do that. And the CRT port should be disabled after the pipe, as we do on other PCH platforms too since commit 1ea56e26 ("drm/i915: Disable CRT port after pipe on PCH platforms") commit 00490c22 ("drm/i915: Consider SPLL as another shared pll, v2.") moved the SPLL disable from the .post_disable() hook to some upper level code, so we can just move the CRT port disabling into the .post_disable() hook. If we still had the non-shared SPLL, it would have needed to be moved into the .post_pll_disable() hook. v2: Actually move the CRT port disable to the .post_disable() hook, and amend the commit message with more details (Paulo) v3: Fix typos in commit message (Paulo) Cc: Paulo Zanoni <przanoni@gmail.com> Signed-off-by:
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Ville Syrjälä authored
Bspec says we should round to closest when computing the LPT-H VGA dotclock, so let's do that. v2: Fix typo in commit message (Paulo) Signed-off-by:
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Ville Syrjälä authored
When we want to use SPLL for FDI we want SSC, which means we have to disable clock bending for the PCH SSC reference (bend and spread are mutually exclusive). So let's turn off bending when we want spread. In case the BIOS enabled clock bending for some reason we'll just turn it off and enable the spread mode instead. Not sure what happens if the BIOS is actually using the bend source for HDMI at this time, but I suppose it should be no worse than what already happens when we simply turn on the spread. We don't currently use the bend source for anything, and only use the PCH SSC reference for the SPLL to drive FDI (always with spread). v2: Fix the %5 vs %10 fumble for SSCDITHPHASE (Paulo) Add 'WARN_ON(steps % 5 != 0)' sanity check (Paulo) Fix typos in commit message (Paulo) Cc: Paulo Zanoni <przanoni@gmail.com> Signed-off-by: -
Mika Kuoppala authored
WaRsDoubleRc6WrlWithCoarsePowerGating should be enabled for all Skylakes. Make it so. Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:
Sagar Arun Kamble <sagar.a.kamble@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449505785-20812-2-git-send-email-mika.kuoppala@intel.comSigned-off-by:
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Mika Kuoppala authored
There is conflicting info between E0 and F0 steppings for this workarounds. Trust more authoritative source and be conservative and extend also for F0. This prevents numerous (>50) gpu hangs with SKL GT4e during piglit run. References: HSD: gen9lp/2134184 Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Signed-off-by:
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- 07 Dec, 2015 6 commits
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Rodrigo Vivi authored
'commit 97173eaf ("drm/i915: PSR: Increase idle_frames")' was a mistake. The special case it tried to cover was already being covered by the DP_PSR_NO_TRAIN_ON_EXIT. So this ended up duplicated. So, instead of reverting that let's take this opportunity and unify the idle_frame definition in a single place so we standardize the access and avoid room for that same mistake again. Few changes with this patch: 1. Instead of just respecting the VBT we set a global minumum with max(). So we are sure that we will avoid corner cases in case VBT is doing something we don't understand. 2. Instead of minimum 5 we use 6. When introducing the idle_frames += 4 case we considered that minimum was 2. All because the off-by-one issue. v2: Unified idle_frame definition. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Maarten Lankhorst authored
wait_vblank is already set in intel_plane_atomic_calc_changes for broadwell, waiting for a double vblank is overkill. Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1447945645-32005-5-git-send-email-maarten.lankhorst@linux.intel.com
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Maarten Lankhorst authored
On skylake some of the registers are only writable when the correct power wells are enabled. Because of this watermarks have to be updated before the crtc turns off, or you get unclaimed register read and write warnings. This patch needs to be modified slightly to apply to -fixes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181Signed-off-by:
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Maarten Lankhorst authored
This removes pre/post_wm_update from intel_crtc->atomic, and creates atomic state for it in intel_crtc. Changes since v1: - Rebase on top of wm changes. Changes since v2: - Split disable_cxsr into a separate patch. Changes since v3: - Move some of the changes to intel_wm_need_update. Signed-off-by:
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Maarten Lankhorst authored
intel_crtc->atomic will be removed later on, move this member to intel_crtc_state. Signed-off-by:
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Zeng Zhaoxiu authored
i915: Replace "hweight8(dev_priv->info.subslice_7eu[i]) != 1" with "!is_power_of_2(dev_priv->info.subslice_7eu[i])" Signed-off-by:
Zeng Zhaoxiu <zhaoxiu.zeng@gmail.com> Signed-off-by:
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- 04 Dec, 2015 9 commits
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Daniel Vetter authored
Signed-off-by: -
Mika Kuoppala authored
Add Skylake Intel Graphics GT4 PCI IDs v2: Rebase Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
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Daniel Vetter authored
This reverts commit 6d65ba94. Mika Kuoppala traced down a use-after-free crash in module unload to this commit, because ring->last_context is leaked beyond when the context gets destroyed. Mika submitted a quick fix to patch that up in the context destruction code, but that's too much of a hack. The right fix is instead for the ring to hold a full reference onto it's last context, like we do for legacy contexts. Since this is causing a regression in BAT it gets reverted before we can close this. Cc: Nick Hoath <nicholas.hoath@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: David Gordon <david.s.gordon@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Alex Dai <yu.dai@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93248Acked-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com>
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Deepak M authored
The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the correct value here. Signed-off-by:
Deepak M <m.deepak@intel.com> Reviewed-by:
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Daniel Vetter authored
This was broken in commit 6a8beeff Author: Wayne Boyer <wayne.boyer@intel.com> Date: Wed Dec 2 13:28:14 2015 -0800 drm/i915: Clean up device info structure definitions and I didn't spot this while reviewing. We really need that CI farm up asap! Reported-by:
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Chris Wilson authored
In commit 2e1b8730 [v4.2] Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Mon Apr 27 13:41:22 2015 +0100 drm/i915: Convert RPS tracking to a intel_rps_client struct we converted the __i915_wait_request() to take a new intel_rps_client struct (rather than having to pass fake drm_i915_file_private structs). However, due to use of passing a void pointer, I didn't spot one callsite in wait-ioctl was passing the wrong pointer. Fwiw, the impact of this bug is zero. Along the rps path, we always first call list_empty(rps) which when we pass in the wrong pointer always evaluates to false and we return early and never chase the invalid pointers. The user visible impact is then wait-ioctl doesn't get the same waitboosting as the other interfaces (set-domain, throttle), which is a performance concern for the *very* few users of the wait interface. There is also a libdrm_intel patch to use the wait-ioctl for drm_intel_bo_wait_rendering() if anyone feels inclined to review libdrm_intel patches. Signed-off-by:
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Daniel Vetter authored
This reverts commit 89f41f4f. It's possible that ->crtc is NULL in here. Noticed by Ville. Signed-off-by:
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Wayne Boyer authored
Beginning with gen7, newer devices repetitively redefine values for the device info structure members. This patch simplifies the structure definitions by grouping member value definitions into the existing GEN7_FEATURES #define and into the new GEN7_LP_FEATURES and HSW_FEATURES #defines. Specifically, GEN_DEFAULT_PIPEOFFSETS and IVB_CURSOR_OFFSETS are added to GEN7_FEATURES and subsequent IVB definitions are simplified. VLV_FEATURES is defined to differentiate and simplify the gen7 low power (LP) devices. HSW_FEATURES is defined and used to simplify all HSW+ devices except for LP. v2: Use VLV_FEATURES for the gen7 low power devices. (Jani) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Takashi Iwai authored
to_intel_crtc() always returns a non-NULL pointer. Signed-off-by:
Takashi Iwai <tiwai@suse.de> Signed-off-by:
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- 03 Dec, 2015 3 commits
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Maarten Lankhorst authored
As the comment indicates this can only fail gracefully when called from compute_config. Fortunately this is now what's happening, so the fixme can be removed and the DRM_ERROR downgraded. Link: http://patchwork.freedesktop.org/patch/msgid/1448360945-5723-3-git-send-email-maarten.lankhorst@linux.intel.comSigned-off-by:
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Alex Goins authored
In intel_prepare_plane_fb, if fb is backed by dma-buf, wait for exclusive fence v2: First commit v3: Remove object_name_lock acquire Move wait from intel_atomic_commit() to intel_prepare_plane_fb() v4: Wait only on exclusive fences, interruptible with no timeout v5: Style tweaks to more closely match rest of file v6: Properly handle interrupted waits v7: No change v8: No change Link: https://patchwork.kernel.org/patch/7704181/Signed-off-by:Alex Goins <agoins@nvidia.com> Signed-off-by:
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Alex Goins authored
If a buffer is backed by dmabuf, wait on its reservation object's exclusive fence before flipping. v2: First commit v3: Remove object_name_lock acquire v4: Move wait ahead of mark_page_flip_active Use crtc->primary->fb to get GEM object instead of pending_flip_obj use_mmio_flip() return true when exclusive fence is attached Wait only on exclusive fences, interruptible with no timeout v5: Move wait from do_mmio_flip to mmio_flip_work_func Style tweaks to more closely match rest of file v6: Change back to unintteruptible wait to match __i915_wait_request due to inability to properly handle interrupted wait. Warn on error code from waiting. v7: No change v8: Test for !reservation_object_signaled_rcu(test_all=FALSE) instead of obj->base.dma_buf->resv->fence_excl Link: https://patchwork.kernel.org/patch/7704181/Signed-off-by:
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