- 19 Feb, 2020 8 commits
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Chris Wilson authored
For dgfx, we do not need to reconfigure the IA/ring frequencies of the main processors as they are distinct devices. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Andi Shyti <andi.shyti@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200219130119.1457693-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Currently, we check that a new context has a clear set of general purpose registers. Add a little bit of hostility by preempting our new context and re-poisoning the GPR to ensure that there is no context leakage from preemption. Signed-off-by:
Ramalingam C <ramalingam.c@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200219123418.1447428-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Check that the CTX_TIMESTAMP is monotonic across context save/restore and upon preemption. References: https://gitlab.freedesktop.org/drm/intel/issues/1233Signed-off-by:
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Chris Wilson authored
Read the rawclk_freq during runtime info probing, prior to its first use in computing the CS timestamp frequency. Then store it in the runtime info, and include it in the debug printouts. Closes: https://gitlab.freedesktop.org/drm/intel/issues/834Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200216163445.555786-1-chris@chris-wilson.co.uk
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Chris Wilson authored
On dgfx, we only use l3cc and not mocs, but we share the table containing both register definitions with Tigerlake. This confuses our selftest that verifies that both sets of registers do contain the values in our tables after various events (idling, reset, activity etc). When constructing the table of register definitions, also include the flags for which registers are valid so that information is computed centrally and available to all callers. Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200218162150.1300405-10-chris@chris-wilson.co.uk
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Jani Nikula authored
Push irq uninstall further up, by splitting i915_driver_modeset_remove() to two, the part with working irqs before irq uninstall, and the part after irq uninstall. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200214135058.7580-2-jani.nikula@intel.com
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Jani Nikula authored
Split intel_modeset_driver_remove() to two, the part with working irqs before irq uninstall, and the part after irq uninstall. Move irq_unintall() closer to the layer it belongs. The error path in i915_driver_modeset_probe() looks obviously weird after this, but remains as good or broken as it ever was. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
spinlock_t is one case where the typedef is to be preferred over struct spinlock. Fixes: 42fb60de ("drm/i915/gem: Don't leak non-persistent requests on changing engines") Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
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- 18 Feb, 2020 7 commits
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Chris Wilson authored
As we have the total runtime known to us, show it when dumping the engine state for debug. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200218162150.1300405-2-chris@chris-wilson.co.uk
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Chris Wilson authored
Always flush the tasklet if we have pending submissions in wait_for_submit(), so that even if we see the HW has started before we process its ack, when we return the execlists state is well defined. Fixes: 06289949 ("drm/i915/selftests: Check for any sign of request starting in wait_for_submit()") Signed-off-by:
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Chris Wilson authored
Just missed setting err along an interruptible error path for the intel_engine_pulse(). Signed-off-by:
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Chris Wilson authored
We only want to wait until the request has been submitted at least once; that is it is either in flight, or has been. References: fcf7df7a ("drm/i915/selftests: Check for the error interrupt before we wait!") Signed-off-by:
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Rafael Antognolli authored
It's not clear whether this workaround is final yet, but the BSpec indicates that userspace needs to set bit 9 of this register on demand: "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA" Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2501Signed-off-by:
Rafael Antognolli <rafael.antognolli@intel.com> [mattrope: Tweaked comment while applying] Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
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Jani Nikula authored
The implicit "dev_priv" local variable use has been a long-standing pain point in the register access macros I915_READ(), I915_WRITE(), POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW(). Replace them with the corresponding new display engine register accessors intel_de_read(), intel_de_write(), intel_de_posting_read(), intel_de_read_fw(), and intel_de_write_fw(). No functional changes. Generated using the following semantic patch: @@ expression REG, OFFSET; @@ - I915_READ(REG) + intel_de_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - POSTING_READ(REG) + intel_de_posting_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE(REG, OFFSET) + intel_de_write(dev_priv, REG, OFFSET) @@ expression REG; @@ - I915_READ_FW(REG) + intel_de_read_fw(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE_FW(REG, OFFSET) + intel_de_write_fw(dev_priv, REG, OFFSET) Reviewed-by:
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Jani Nikula authored
The implicit "dev_priv" local variable use has been a long-standing pain point in the register access macros I915_READ(), I915_WRITE(), POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW(). Replace them with the corresponding new display engine register accessors intel_de_read(), intel_de_write(), intel_de_posting_read(), intel_de_read_fw(), and intel_de_write_fw(). No functional changes. Generated using the following semantic patch: @@ expression REG, OFFSET; @@ - I915_READ(REG) + intel_de_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - POSTING_READ(REG) + intel_de_posting_read(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE(REG, OFFSET) + intel_de_write(dev_priv, REG, OFFSET) @@ expression REG; @@ - I915_READ_FW(REG) + intel_de_read_fw(dev_priv, REG) @@ expression REG, OFFSET; @@ - I915_WRITE_FW(REG, OFFSET) + intel_de_write_fw(dev_priv, REG, OFFSET) Reviewed-by:
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- 17 Feb, 2020 6 commits
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Chris Wilson authored
The ringbuffer's vma is expected to be in the GGTT and that is now being checked, so make sure the mocked ring declares it so. Signed-off-by:
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Chris Wilson authored
Without selftests enabled, I915_SELFTEST_ONLY becomes a dummy, generating a bare '0'. This causes the compiler to complain about a useless line, and while we could use I915_SELFTEST_DECLARE instead, it is a bit messier. Move the selftest-only code to a helper and make that conditional on having selftests enabled. Reported-by:
kbuild test robot <lkp@intel.com> Signed-off-by:
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Jani Nikula authored
Prefer intel_uncore_* over I915_READ, I915_WRITE, and POSTING_READ. Reviewed-by:
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Jani Nikula authored
i915_drv.c is a fairly big file, and having very specific vlv/chv suspend/resume code in it is a distraction. Split it out to a new vlv_suspend.[ch] file. Reviewed-by:
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Jani Nikula authored
We've moved from bugzilla to gitlab. Cc: stable@vger.kernel.org Reviewed-by:
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Jani Nikula authored
We've moved from bugzilla to gitlab. Cc: stable@vger.kernel.org Reviewed-by:
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- 16 Feb, 2020 2 commits
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Chris Wilson authored
Since we use a HW readback or estimation of the CS timestamp frequency, sometimes it may result in 0. Avoid the division-by-zero in computing its reciprocal, the timestamp period. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200216161746.500258-1-chris@chris-wilson.co.uk
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Tvrtko Ursulin authored
GPU saves accumulated context runtime (in CS timestamp units) in PPHWSP which will be useful for us in cases when we are not able to track context busyness ourselves (like with GuC). Keep a copy of this in struct intel_context from where it can be easily read even if the context is not pinned. v2: (Chris) * Do not store pphwsp address in intel_context. * Log CS wrap-around. * Simplify calculation by relying on integer wraparound. v3: * Include total/avg in traces and error state for debugging Signed-off-by:
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- 15 Feb, 2020 4 commits
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Ville Syrjälä authored
Currently when we load the driver we set distrust_bios_wm=true, which will cause active_pipe_changes to get flagged even when we're not toggling any pipes on/off. The reason being that we want to fully redistribute the dbuf among the active pipes and ignore whatever state the firmware left behind. Unfortunately when the code flags active_pipe_changes it doesn't set state->modeset to true, which means the hardware dbuf state won't actually get updated. Hence the hardware and software states go out of sync, which can result in planes trying to use a disabled dbuf slice. Suprisingly that only seems to corrupt the display rather than making the whole display engine keel over. Let's fix this for now by flagging state->modeset whenever distrust_bios_wm is set. Eventually we'll likely want to rip out all of this mess and introduce proper statye tracking for dbuf. But that requires more work. Toss in a FIXME to that effect. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: ff2cd863 ("drm/i915: Correctly map DBUF slices to pipes") Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by:
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Jani Nikula authored
We lack full state readout of DSC config, which may lead to DSC enable using a config that's all zeros, failing spectacularly. Force full modeset and thus compute config at probe to get a sane state, until we implement DSC state readout. Any fastset that did appear to work with DSC at probe, worked by coincidence. [1] is an example of a change that triggered the issue on TGL DSI DSC. [1] http://patchwork.freedesktop.org/patch/msgid/20200212150102.7600-1-ville.syrjala@linux.intel.com Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: stable@vger.kernel.org Fixes: fbacb15e ("drm/i915/dsc: add basic hardware state readout support") Acked-by:
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Stanislav Lisovskiy authored
TGL BIOS seems to enable both DBuf slices ocasionally, depending how many displays are connected, while i915 according to BSpec was powering on S1 DBuf slice, until a modeset was done. This was causing a brief flash during the boot as we were disabling slice, previously used by BIOS with that. To prevent this, now we are ensuring tht we are enabling _at least_ one slice, but if there are more, let's not power them off. Fixes: ff2cd863 ("drm/i915: Correctly map DBUF slices to pipes") Reviewed-by:
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José Roberto de Souza authored
Commit 1c9d2eb2 ("drm/i915: move intel_dp_set_m_n() to encoder for DDI platforms") moved the intel_dp_set_m_n() from hsw_crtc_enable() to intel_ddi_pre_enable_dp() but it missed add it to intel_mst_pre_enable_dp() causing MST slaves to not work. v2: Not setting intel_ddi_set_dp_msa() twice for MST master Fixes: 1c9d2eb2 ("drm/i915: move intel_dp_set_m_n() to encoder for DDI platforms") Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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- 14 Feb, 2020 3 commits
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Chris Wilson authored
Sometimes the error interrupt can fire even before we have seen the request go active -- in which case, we end up waiting until the timeout as the request is already completed. Double check for this case! Signed-off-by:
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Jani Nikula authored
The i915_debugfs.c has grown more than a little unwieldy. Split out the display related debugfs code to a file of its own under display/, initialized with a separate call. No functional changes. v2: - Also moved i915_frontbuffer_tracking, i915_gem_framebuffer, i915_power_domain_info, i915_dmc_info, i915_ipc_status (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
The DMC firmware is about display. Move the handling under display. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by:
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- 13 Feb, 2020 6 commits
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Jani Nikula authored
Prefer i915 over dev_priv where possible. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Move vga switcheroo and dsm handler register later in i915_driver_register(), and unregister in i915_driver_unregister(). The dsm handler unregister is a nop, and is only added for completeness. My unsubstantiated suspicion is that the vga switcheroo state change would not work as early as we register the hooks currently. In any case exposing the interfaces to the world only after we've got everything set up seems prudent. Also replace the error handling in vga switcheroo register with a simple error message. This is done at the same time due to lack of error propagation from i915_driver_register(). Cc: Lukas Wunner <lukas@wunner.de> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by:
Lukas Wunner <lukas@wunner.de> Signed-off-by:
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Jani Nikula authored
drm->dev_private is to be avoided. Use to_i915() on the struct drm_device pointer instead. Rename the affected local dev_priv variables to i915 while at it. Cc: Wambui Karuga <wambui.karugax@gmail.com> Reviewed-by:
Wambui Karuga <wambui.karugax@gmail.com> Signed-off-by:
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Chris Wilson authored
Originally, I did not expect having to rewind a context upon timeslicing: the point was to replace the executing context with a non-executing one! However, given a second context that depends on requests from the first, we may have to split the requests along the first context to execute the second, causing us to partially replay the first context and so have to rewind its RING_TAIL. References: 5ba32c7b ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL") Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200213140150.3639027-1-chris@chris-wilson.co.uk
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Chris Wilson authored
With debugging turned off, we have to tell the compiler not to warn about the unused debug locals. Signed-off-by:
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Mika Kuoppala authored
This is in mcr range of register, thus we can only verify it through mmio. Use engine wa list with mcr range verification skip. Fixes: 0db1a5f8 ("drm/i915: Implement Wa_1607090982") Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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- 12 Feb, 2020 4 commits
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Chris Wilson authored
Show the ring/request/context state if we see what we believe is an early CS completion. Signed-off-by:
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Chris Wilson authored
Make sure we avoid ending up with a phys_sz of 0, or for phys_sz to be larger than the actual size. Closes: https://patchwork.freedesktop.org/series/73320/Signed-off-by:
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Chris Wilson authored
Apply vast quantities of poison and not tell anyone to see if we fall for the trap of using a stale RING_HEAD. References: 42827350 ("drm/i915/gt: Avoid resetting ring->head outside of its timeline mutex") Signed-off-by:
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Chris Wilson authored
On retiring the request, we should not re-use these elements in the ring (at least not until we fill the ringbuffer and knowingly reuse the space). Leave behind some poison to (hopefully) trap ourselves if we make a mistake. Suggested-by:
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