- 15 May, 2023 40 commits
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Ian Rogers authored
Check a bogus PMU fails and that a known PMU succeeds. Limit to PMUs known cpu, cpu_atom and armv8_pmuv3_0 ones. Signed-off-by:
Ian Rogers <irogers@google.com> Tested-by:
Kan Liang <kan.liang@linux.intel.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Ahmad Yasin <ahmad.yasin@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Edward Baker <edward.baker@intel.com> Cc: Florian Fischer <florian.fischer@muhq.space> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Kang Minchul <tegongkang@gmail.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Rob Herring <robh@kernel.org> Cc: Samantha Alt <samantha.alt@intel.com> Cc: Stephane Eranian <eranian@google.com> Cc: Sumanth Korikkar <sumanthk@linux.ibm.com> Cc: Suzuki Poulouse <suzuki.poulose@arm.com> Cc: Thomas Richter <tmricht@linux.ibm.com> Cc: Tiezhu Yang <yangtiezhu@loongson.cn> Cc: Weilin Wang <weilin.wang@intel.com> Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: Yang Jihong <yangjihong1@huawei.com> Link: https://lore.kernel.org/r/20230513063447.464691-1-irogers@google.comSigned-off-by:
Arnaldo Carvalho de Melo <acme@redhat.com>
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Arnaldo Carvalho de Melo authored
perf build: Don't use -ftree-loop-distribute-patterns and -gno-variable-location-views in the python feature test when building with clang-13 Using -ftree-loop-distribute-patterns and -gno-variable-location-views in the python feature test when building with clang-16 results in: 16 80.04 clearlinux:latest : FAIL clang version 16.0.1 clang-16: error: unknown argument: '-gno-variable-location-views' clang-16: error: unknown argument: '-gno-variable-location-views' clang-16: error: optimization flag '-ftree-loop-distribute-patterns' is not supported [-Werror,-Wignored-optimization-argument] clang-16: error: optimization flag '-ftree-loop-distribute-patterns' is not supported [-Werror,-Wignored-optimization-argument] error: command '/usr/sbin/clang' failed with exit code 1 Noticed when building on a docker.io/library/clearlinux:latest container. Signed-off-by: -
Ian Rogers authored
Move to print-events.c and make static. Signed-off-by:
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Ian Rogers authored
Now that hybrid bugs are fixed sufficient to run TopdownL1 metrics, don't implicitly disable them for hybrid. Signed-off-by:
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Ian Rogers authored
Ids/events from a metric are turned into an event string and parsed; setup_metric_events matches the id back to the parsed evsel. With hybrid the same event may exist on both PMUs with the same name and be being used by metrics at the same time. A metric on cpu_core therefore shouldn't match against evsels on cpu_atom, or the metric will compute the wrong value. Make the matching sensitive to the PMU being parsed. Signed-off-by:
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Ian Rogers authored
Don't rewrite metrics across PMUs as the result events likely won't be found. Identify metrics with a pair of PMU name and metric name. Signed-off-by:
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Ian Rogers authored
Fix the metrics tma_memory_bound on alderlake cpu_core and tma_microcode_sequencer on alderlake cpu_atom, where metrics had be rewritten across PMUs. Fix MEM_BOUND_STALLS_AT_RET_CORRECTION which is an aux metric but lacks a hash prefix. Add PMU prefixes for cpu_core/cpu_atom events to avoid wildcard opening the events. Signed-off-by:
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Ian Rogers authored
Wire up the --cputype value to limit which metrics are parsed. Signed-off-by:
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Ian Rogers authored
Hybrid systems may define the same metric for different PMUs, this can cause confusion of events. To avoid this make the referenced metric searches PMU specific, matching that in the table. Signed-off-by:
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Ian Rogers authored
On hybrid systems the topdown events don't share a fixed counter on the atom core, so they don't require the sorting the perf metric supporting PMUs do. Signed-off-by:
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Ian Rogers authored
Bring back the behavior of not auto-merging hybrid events by delegating to a test in pmu. Signed-off-by:
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Ian Rogers authored
Avoid the parser error: ''' $ perf stat -e 'cycles/name=l1d/' true event syntax error: 'cycles/name=l1d/' \___ parser error ''' by combining the name and legacy cache cases in the parser. Signed-off-by: -
Ian Rogers authored
Avoid the parser error: ''' $ perf stat -e 'cycles/name=name/' true event syntax error: 'cycles/name=name/' \___ parser error ''' by turning the term back to a string if it is on the right. Add PMU and generic parsing tests. Signed-off-by: -
Ian Rogers authored
An event like "cpu/instructions/" typically parses due to there being a sysfs event called instructions. On hybrid recursive parsing means that the hardware event is encoded in the attribute, with the PMU being placed in the high bits of the config: ''' $ perf stat -vv -e 'cpu_core/cycles/' true ... ------------------------------------------------------------ perf_event_attr: size 136 config 0x400000000 sample_type IDENTIFIER read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING disabled 1 inherit 1 enable_on_exec 1 exclude_guest 1 ------------------------------------------------------------ ''' Make this behavior the default by adding a new term type and token for hardware events. The token gathers both the numeric config and the parsed name, so that if the token appears like "cycles/name=cycles/" then the token can be handled like a name. The numeric value isn't sufficient to distinguish say "cpu-cycles" from "cycles". Extend the parse-events test so that all current non-PMU hardware parsing tests, also test with the PMU cpu - more than half the change. Signed-off-by:
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Ian Rogers authored
Remove assumptions of just 1 core PMU. Signed-off-by:
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Ian Rogers authored
Rather than limit the --cputype argument for "perf list" and "perf stat" to hybrid PMUs of just cpu_atom and cpu_core, allow any PMU. Note, that if cpu_atom isn't mounted but a filter of cpu_atom is requested, then this will now fail. As such a filter would never succeed, no events can come from that unmounted PMU, then this behavior could never have been useful and failing is clearer. Signed-off-by:
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Ian Rogers authored
To support the cputype argument added to "perf stat" for hybrid it is necessary to filter events during wildcard matching. Add a scanner argument for the filter and checking it when wildcard matching. Signed-off-by:
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Ian Rogers authored
Use the typed parse_state rather than void* _parse_state when available. Signed-off-by:
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Ian Rogers authored
The event parser no longer needs to recurse in case of a legacy cache event in a PMU, the necessary wild card logic has moved to perf_pmu__supports_legacy_cache and perf_pmu__supports_wildcard_numeric. Signed-off-by:
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Ian Rogers authored
Legacy raw events like r1a open as PERF_TYPE_RAW on non-hybrid systems and on each hybrid PMU on hybrid systems. Rather than iterate hybrid PMUs add a perf_pmu__supports_wildcard_numeric function that says when a numeric event should be opened upon it. If the parsed event specifies the type of the PMU then don't wildcard match PMUs, use the specified PMU type. Signed-off-by:
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Ian Rogers authored
Mirroring parse_events_add_cache, list the legacy name alongside its alias with the PMU. Remove the now unnecessary hybrid logic. Note, the alias output removes the event type descriptor, so: L1-dcache-loads [Hardware cache event] becomes: L1-dcache-loads OR cpu/L1-dcache-loads/ Signed-off-by:
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Ian Rogers authored
It is inconsistent that "perf stat -e instructions-retired" wildcard opens on all PMUs while legacy cache events like "perf stat -e L1-dcache-load-miss" do not. A behavior introduced by hybrid is that a legacy cache event like L1-dcache-load-miss should wildcard open on all hybrid PMUs. Previously hybrid would call to is_event_supported for each PMU, a failure of which results in the event not being added. This isn't done in this case as the parser should just create perf_event_attr and the later open should fail, or the counter give "<not counted>". If this wants to be avoided then the PMU can be named with the event. Signed-off-by:
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Ian Rogers authored
Allow a legacy cache event to be both, for example, "L1-dcache-load-miss" and "cpu/L1-dcache-load-miss/" by introducing a new legacy cache term type. The term type is processed in config_term_pmu, setting both the type in perf_event_attr and the config. The code to determine the config is factored out of parse_events_add_cache and shared. If the PMU doesn't support legacy events, currently just core/hybrid PMUs do, then the term is treated like a PE_NAME term - as before. If only terms are being parsed, such as for perf_pmu__new_alias, then the PE_LEGACY_CACHE token is always parsed as PE_NAME. Signed-off-by:
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Ian Rogers authored
Assert hybrid extended types are as expected. Signed-off-by:
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Ian Rogers authored
Don't assume evlist order. Switch to a loop rather than depend on evlist order for raw events test. Update hybrid event expectations. Previous values were based on parsing legacy hardware events from sysfs, update to the correct PMU specific legacy values. Signed-off-by:
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Ian Rogers authored
The tests use x86 hybrid specific PMUs. Signed-off-by:
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Ian Rogers authored
The event parser needs to handle two special cases: 1) legacy events like L1-dcache-load-miss. These event names don't appear in JSON or sysfs, and lookup tables are used for the config value. 2) raw events where 'r0xead' is the same as 'read' unless the PMU has an event called 'read' in which case the event has priority. The previous parser to handle these cases would scan all PMUs for components of event names. These components would then be used to classify in the lexer whether the token should be part of a legacy event, a raw event or an event. The grammar would handle legacy event tokens or recombining the tokens back into a regular event name. The code wasn't PMU specific and had issues around events like AMD's branch-brs that would fail to parse as it expects brs to be a suffix on a legacy event style name: $ perf stat -e branch-brs true event syntax error: 'branch-brs' \___ parser error This change removes processing all PMUs by using the lexer in the form of a regular expression matcher. The lexer will return the token for the longest matched sequence of characters, and in the event of a tie the first. The legacy events are a fixed number of regular expressions, and by matching these before a name token its possible to generate an accurate legacy event token with everything else matching as a name. Because of the lexer change the handling of hyphens in the grammar can be removed as hyphens just become a part of the name. To handle raw events and terms the parser is changed to defer trying to evaluate whether something is a raw event until the PMU is known in the grammar. Once the PMU is known, the events of the PMU can be scanned for the 'read' style problem. A new term type is added for these raw terms, used to enable deferring the evaluation. While this change is large, it has stats of: 170 insertions(+), 436 deletions(-) the bulk of the change is deleting the old approach. It isn't possible to break apart the code added due to the dependencies on how the parts of the parsing work. Signed-off-by: -
Ian Rogers authored
The strlist in print_hwcache_events holds the event names as they are generated, and then it is iterated and printed. This is unnecessary and each event can just be printed as it is processed. Rename the variable i to res, to be more intention revealing and consistent with other code. Signed-off-by:
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Ian Rogers authored
Change add_event to always set pmu_name when possible as not all code checks both pmu->name and evsel->pmu_name, for example, uniquify_counter in stat-display.c. Signed-off-by:
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Ian Rogers authored
Set attr.type to PMU type early so that later terms can override the value. Setting the value in perf_pmu__config means that earlier steps, like config_term_pmu, can override the value. Signed-off-by:
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Ian Rogers authored
Opening hardware names and a legacy cache event on a hybrid PMU opens it on each PMU. Parsing and checking indexes fails, as the parsed index is double the expected. Avoid checking the index by just comparing the names immediately after the parse. This change removes hard coded hybrid logic and removes assumptions about the expansion of an event. On hybrid the PMUs may or may not support an event and so using a distance isn't a consistent solution. Reviewed-by:
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Ian Rogers authored
test__checkevent_config_cache checks the parsing of "L1-dcache-misses/name=cachepmu/". Don't just check that the name is set correctly, also validate the rest of the perf_event_attr for L1-dcache-misses. Reviewed-by:
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Ian Rogers authored
Add helper to test the config of an evsel. Dependent on the type of the evsel, mask the config so that high-bits containing the extended PMU type are ignored. Signed-off-by:
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Ian Rogers authored
Rather than skip all tests in test__events_pmu if PMU cpu isn't present, use the per-test valid test. This allows the running of software PMU tests on hybrid and arm systems. Reviewed-by:
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Ian Rogers authored
Parse events for all PMUs, and not just cpu, in test "Parsing of all PMU events from sysfs". Signed-off-by:
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Ian Rogers authored
Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71Signed-off-by:
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Ian Rogers authored
Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71Signed-off-by:
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Ian Rogers authored
Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71Signed-off-by:
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Ian Rogers authored
Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71Signed-off-by:
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Ian Rogers authored
Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71Signed-off-by:
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