- 13 Jul, 2022 6 commits
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Likun Gao authored
Enable soft reset for gfx 11. V2: enable both gfx v11.0.0 and gfx v11.0.2. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Likun Gao authored
Support GFX soft reset for gfx v11. V3: use ib test check soft reset. V4: squash in unused variable fix (Alex) Signed-off-by:
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Chris Park authored
[Why] Status flags definition is reduced to read less bytes in SCDC transaction for status update. [How] Reduce definition of reserved bytes from 3 to 1 for status update. Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Solomon Chiu <solomon.chiu@amd.com> Signed-off-by:
Chris Park <chris.park@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Prike Liang authored
On the GC 10.3.7 platform the initial MEC release version #3 can support atomic operation,so need correct and set its MEC atomic support version to #3. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] Ideally link capability should be independent from the link configuration that we decide to use in enable link. Otherwise if link capability is changed after validation has completed, we could end up enabling a link configuration with invalid configuration. This would lead to over link bandwidth subscription or in the extreme case causes us to enable HPO link to a DIO stream. [how] Add a new struct in pipe ctx called link config. This structure will contain link configuration to enable a link. It will be populated during map pool resources after we validate link bandwidth. Remove the reference of verified link cap during enable link process and use link config in pipe ctx instead. Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Fangzhi Zuo authored
[why] First MST sideband message returns AUX_RET_ERROR_HPD_DISCON on certain intel platform. Aux transaction considered failure if HPD unexpected pulled low. The actual aux transaction success in such case, hence do not return error. [how] Not returning error when AUX_RET_ERROR_HPD_DISCON detected on the first sideband message. v2: squash in additional DMI entries v3: squash in static fix Signed-off-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Acked-by:
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- 12 Jul, 2022 14 commits
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Eric Huang authored
To expose unified memory for ctx save/resotre area feature availablity to libhsakmt. Proposed userspace: https://patchwork.freedesktop.org/series/106218/Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Samson Tam authored
[Why] When playing NV12 1080p MPO video, it is pipe splitting so we see two pipes in fullscreen and four pipes in windowed mode. Pipe split is happening because we are setting MaximumMPCCombine = 1 [How] Algorithm for MaximumMPCCombine has extra conditions we do not need. Use DCN31 algorithm instead Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Ilya Bakoulin authored
[Why] Black screen encountered when disabling Freesync through OSD on some displays. [How] Set the should_disable flag when new top pipe has no plane state to ensure that pipes get cleaned up. Reviewed-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Tested-by:
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Robin Chen authored
[Why] Some specific sink is not able to support PSRSU when DSC is turned on. For this case, fall-back to use PSR1. Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Robin Chen <po-tchen@amd.com> Tested-by:
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Wayne Lin authored
[Why] When unplug one sst monitor from a mst hub and plug in the same port with another sst monitor, we don't read the corresponding edid. That's because we detect there is already an edid stored in aconnector->edid which is a stale one. [How] Clean up aconnector->edid when unplug mst connector. Reviewed-by:
Hersen Wu <hersen.wu@amd.com> Acked-by:
Wayne Lin <Wayne.Lin@amd.com> Tested-by:
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Samson Tam authored
[Why] In single display configuration, windowed MPO does not work with ODM combine. [How] For ODM + MPO window on one half of ODM, only 3 pipes should be allocated and scaling parameters adjusted to handle this case. Otherwise, we use 4 pipes. Move copy_surface_update_to_plane() before dc_add_plane_to_context() so that it gets the updated rect information when setting up the pipes. Add dc_check_boundary_crossing_for_windowed_mpo_with_odm() to force a full update when we cross a boundary requiring us to reconfigure the number of pipes between 3 and 4 pipes. Set config.enable_windowed_mpo_odm to true when we have the debug.enable_single_display_2to1_odm_policy set to true. Don't fail validating ODM with windowed MPO if config.enable_windowed_mpo_odm is true. Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Saaem Rizvi authored
[WHY] Assert statements causing several bugs on Linux DM [HOW] Removing assert statement for Linux DM (ASSERT(result == VBIOSSMC_Result_OK)). Also adding logging statements for setting dcfclk. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=216092 Fixes: c1b972a1 ("drm/amd/display: Insert pulling smu busy status before sending another request") Reviewed-by:
Gabe Teeger <Gabe.Teeger@amd.com> Acked-by:
Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Tested-by:
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Muhammad Ansari authored
[WHY] Needed a helper function for ALPM DPCD initialization [HOW] Refactoring to put ALPM initialization in a helper function Reviewed-by:
Muhammad Ansari <muansari@amd.com> Tested-by:
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Wesley Chalmers authored
[WHY] Certain DP 2.0 modes may fail validation if DP 2.0 is not considered for ODM combine. Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by:
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Alvin Lee authored
[Description] Exit SubVP if MPO is in use since SubVP + MPO together is not supported. - Don't add SubVP at validation time if we see MPO is in use Issues fixed in the SubVP / MPO transition: 1. Enable phantom pipes in post unlock function to prevent underflow when an active pipe is being transitioned to be a phantom pipe (VTG updates take place right away). Also must wait for VUPDATE of the main pipe to complete first 2. Don't wait for MPCC idle when transitioning a phantom pipe to an actual pipe. MPCC_STATUS is never asserted due to OTG being off for phantom pipes 3. When transitioning an active pipe to phantom, program DET right away (same as disabling the pipe) or the DET update will only take when the phantom pipe is enabled which can cause DET allocation errors. 4. For K1/K2 programming of phantom pipes, use same settings as the main pipe. Also don't program K1 / K2 = 0xF ever since the field is only 1 / 2 bits wide. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Jack Xiao authored
Set corresponding ready flag for mes ring when enable or disable mes ring. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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xinhui pan authored
That has been done in BO release notify. Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Alex Deucher authored
For GMC 10 parts which support scatter/gather display (display from system memory), we should allocate a larger gart size to better handler larger displays. This mirrors what we already do for GMC 9 parts. v2: fix typo (Alex) Acked-by:
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Jack Xiao authored
Need reserve buffers before unmap mes ctx bo va. v2: fix removal of dma_resv_excl_fence() (Alex) v3: fix dma_resv_usage (Alex) Signed-off-by:
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- 08 Jul, 2022 6 commits
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Jack Xiao authored
For some cases (accessing registers, unmap legacy queue), it needs access mes in atomic context. Use spinlock to protect agaist mes ring buffer race condition. Signed-off-by:
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Kenneth Feng authored
drop the thermal_controller_type check since it's not relevant. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Kenneth Feng authored
fixed the issue: gpu runs in dc mode but it is expected to be in ac mode. this causes the lower performance on smu_v13_0 Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Output Data Mapping is a power saving feature that allows us to run at reduced DPP and DISP clocks compared to what could be achieved with a single pipe. Set the default policy for single display use case to use 2 to 1 ODM combine. The options are queried by DC and appropriate register programming sequence is initiated to enable this feature. Fixes: 235c6763 ("drm/amd/display: add DCN32/321 specific files for Display Core") Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] Add a missing callback to set DIG FIFO output pixel mode. This is used when ODM combine is activated. Fixes: 235c6763 ("drm/amd/display: add DCN32/321 specific files for Display Core") Signed-off-by:
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Alex Deucher authored
There are several things wrong here. First, none of these numbers are FP, so there is no need to cast to double. Next make sure to use proper 64 bit division helpers. Fixes: 85f4bc0c ("drm/amd/display: Add SubVP required code") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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- 07 Jul, 2022 14 commits
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Yang Li authored
Eliminate the follow smatch warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:405 get_bios_object_from_path_v3() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:611 bios_parser_get_hpd_info() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:818 bios_parser_get_device_tag() warn: inconsistent indenting drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.c:1599 bios_parser_is_device_id_supported() warn: inconsistent indenting Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Alex Deucher authored
Need to protect FP DMCUB code with CONFIG_DRM_AMD_DC_DCN. Fixes build failures like the following on arm64: ERROR: modpost: "__floatunsidf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__divdf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "fma" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__adddf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__fixdfsi" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__muldf3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__floatsidf" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "__fixunsdfsi" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Fixes: 85f4bc0c ("drm/amd/display: Add SubVP required code") Reported-by:
Nathan Chancellor <nathan@kernel.org> Tested-by:
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Stylon Wang authored
[Why] Changes from "Fix for dmub outbox notification enable" need to land in DM or DMUB outbox notification would be disabled. [How] Enable outbox notification only after interrupt are enabled and IRQ handlers registered. Any pending notification will be sent by DMUB once outbox notification is enabled. Fixes: ed720870 ("drm/amd/display: Fix for dmub outbox notification enable") Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Acked-by:
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xinhui pan authored
Queue would be freed when create_queue_cpsch fails So lets do queue cleanup otherwise various list and memory issues happen. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Mateusz Jończyk authored
I was getting the following message on boot on Linux 5.19-rc5: radeon 0000:01:05.0: vram limit (0) must be a power of 2 (I didn't use any radeon.vramlimit commandline parameter). This is caused by commit 8c2d34eb ("drm/radeon: use kernel is_power_of_2 rather than local version") which removed radeon_check_pot_argument() and converted its users to is_power_of_2(). The two functions differ in its handling of 0, which is the default value of radeon_vram_limit: radeon_check_pot_argument() "incorrectly" considered it a power of 2, while is_power_of_2() does not. An appropriate conditional silences the warning message. It is not necessary to add a similar test to other callers of is_power_of_2() in radeon_device.c. The matching commit in amdgpu: commit 76117507 ("drm/amdgpu: use kernel is_power_of_2 rather than local version") is unaffected by this bug. Tested on Radeon HD 3200. Not ccing stable, this is not serious enough. Fixes: 8c2d34eb ("drm/radeon: use kernel is_power_of_2 rather than local version") Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Jonathan Gray <jsg@jsg.id.au> Signed-off-by:Mateusz Jończyk <mat.jonczyk@o2.pl> Signed-off-by:
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Guo Zhengkui authored
Remove a repeated "#include <drm/drm_print.h>" Reviewed-by:
Guo Zhengkui <guozhengkui@vivo.com> Signed-off-by:
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Zhongjun Tan authored
Remove duplicated argument to || Signed-off-by:
Zhongjun Tan <tanzhongjun@coolpad.com> Signed-off-by:
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Alex Deucher authored
It's not used outside of dcn30_resource.c. Reported-by:
kernel test robot <lkp@intel.com> Reviewed-by:
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Alex Deucher authored
Fixes the following: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn32/dcn32_hwseq.c:428:33: warning: variable 'old_pipe' set but not used Reported-by:
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Eric Huang authored
It is to avoid unnecessary queue eviction when range is not mapped to gpu. Signed-off-by:
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Evan Quan authored
[Why] The return value indicates whether the operation(disable/enable) succeeded or not. The existing logic reports wrong result even if the disablement was performed successfully. That will make succeeding reenablement abandoned as dc->idle_optimizations_allowed is always true. [How] Correct the return value to reflect the real result of disablement. Fixes: 235c6763 ("drm/amd/display: add DCN32/321 specific files for Display Core") Signed-off-by:
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Aurabindo Pillai authored
[Why&How] The debug option to disable idle power optimization can be dropped Fixes: 235c6763 ("drm/amd/display: add DCN32/321 specific files for Display Core") Signed-off-by:
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Eric Huang authored
Adding always evict queues when flag is set to KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED as if XNACK off. Signed-off-by:
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Eric Huang authored
It is to add new option for always keeping gpu mapping. Signed-off-by:
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