- 06 Mar, 2023 7 commits
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Christian König authored
We have a wait in the amdgpu_bo_kmap() code for quite a while now, so waiting here isn't needed any more. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Candice Li authored
Support EccInfoTable which includes umc ras error count and error address. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by:
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Candice Li authored
Don't need to query error count and error address on harvest umc nodes. v2: Fix code bug, use active_mask instead of harvsest_config and remove unnecessary argument in LOOP macro. v3: Leave adev->gmc.num_umc unchanged. Signed-off-by:Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Kun Liu authored
add static prefix for vangogh_set_apu_thermal_limit function Signed-off-by:
Kun Liu <Kun.Liu2@amd.com> Reported-by:
kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202303010827.c2N0yBGT-lkp@intel.comReviewed-by:
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leiyaoyao authored
Do not clear kiq position in RLC_CP_SCHEDULER so that CP could perform IDLE-SAVE after VF fini. Otherwise it could cause GFX hang if another Win guest is rendering. Signed-off-by:
leiyaoyao <yaoyao.lei@amd.com> Acked-by:
ZhenGuo Yin <zhenguo.yin@amd.com> Signed-off-by:
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Harry Wentland authored
This is useful to understand the bpc defaults and support of a driver. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Cc: Pekka Paalanen <ppaalanen@gmail.com> Cc: Sebastian Wick <sebastian.wick@redhat.com> Cc: Vitaly.Prosyak@amd.com Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Joshua Ashton <joshua@froggi.es> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: dri-devel@lists.freedesktop.org Cc: amd-gfx@lists.freedesktop.org Reviewed-By:
Joshua Ashton <joshua@froggi.es> Link: https://patchwork.freedesktop.org/patch/msgid/20230113162428.33874-3-harry.wentland@amd.comSigned-off-by:
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Harry Wentland authored
The EDID of an HDR display defines EOTFs that are supported by the display and can be set in the HDR metadata infoframe. Userspace is expected to read the EDID and set an appropriate HDR_OUTPUT_METADATA. In drm_parse_hdr_metadata_block the kernel reads the supported EOTFs from the EDID and stores them in the drm_connector->hdr_sink_metadata. While doing so it also filters the EOTFs to the EOTFs the kernel knows about. When an HDR_OUTPUT_METADATA is set it then checks to make sure the EOTF is a supported EOTF. In cases where the kernel doesn't know about a new EOTF this check will fail, even if the EDID advertises support. Since it is expected that userspace reads the EDID to understand what the display supports it doesn't make sense for DRM to block an HDR_OUTPUT_METADATA if it contains an EOTF the kernel doesn't understand. This comes with the added benefit of future-proofing metadata support. If the spec defines a new EOTF there is no need to update DRM and an compositor can immediately make use of it. Bug: https://gitlab.freedesktop.org/wayland/weston/-/issues/609 v2: Distinguish EOTFs defind in kernel and ones defined in EDID in the commit description (Pekka) v3: Rebase; drm_hdmi_infoframe_set_hdr_metadata moved to drm_hdmi_helper.c Signed-off-by:
Pekka Paalanen <pekka.paalanen@collabora.com> Reviewed-By:
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- 28 Feb, 2023 31 commits
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Aric Cyr authored
This version brings along the following: - Correct DML calculation - Extend Freesync over Pcon support - Fixes in pstate hang and more - Code cleanup for dc_link.h and dc_link.c Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] The newer commit sequence on DCN32 onwards did not finish clock optimization sequence since the newer sequence did not end up calling dc_post_update_surfaces_to_stream() which resets dc->optimized_required. Call this function before passing control on to the new commit sequence. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Aric Cyr authored
[why] While bandwidth optimizations are pending, it's possible a pstate change will occur. During this time, VSYNC handler should not also try to update DRR parameters causing pstate hang [how] Do not adjust DRR if optimize bandwidth is set. Reviewed-by:
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Aric Cyr authored
[why] If OTG is not active, waiting for blank completion will always fail and timeout resulting in unnecessary driver delays. [how] Check that OTG is enabled before waiting for blank. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
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Samson Tam authored
[Why] In disable_dangling_plane, for phantom pipes, we enable OTG so disable programming gets the double buffer update. But this causes an underflow to occur. [How] Enable DPG prior to enabling OTG. Reviewed-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Wenjing Liu authored
[why] We kept an empty dc_link.c file due to external build dependency. Now the last build dependency has been removed. We can safely delete this file. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Paul Hsieh authored
[Why] In 2560x1440@240p eDP panel, some use cases will enable MPC combine with RGB MPO then underflow happened. This case is not allowed from HW formula. [How] Correct eDP, DP and DP2 output bpp calculation to align HW formula. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Paul Hsieh <Paul.Hsieh@amd.com> Tested-by:
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bobzhou authored
This patch is used to fix following compilation issue with legacy gcc error: ‘for’ loop initial declarations are only allowed in C99 mode for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) { Signed-off-by:bobzhou <bob.zhou@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Felix Kuehling authored
Exports a DMA buf fd of a given KFD buffer handle. This is intended for being able to import KFD BOs into GEM contexts to leverage the amdgpu_bo_va API for more flexible virtual address mappings. It will also be used for the new upstreamable RDMA solution coming to UCX and RCCL. The corresponding user mode change (Thunk API and kfdtest) is here: https://github.com/fxkamd/ROCT-Thunk-Interface/commits/fxkamd/dmabufSigned-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Xiaogang Chen <Xiaogang.Chen@amd.com> Signed-off-by:
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Felix Kuehling authored
Use proper amdgpu_gem_prime_import function to handle all kinds of imports. Remember the dmabuf reference to enable proper multi-GPU attachment to multiple VMs without erroneously re-exporting the underlying BO multiple times. Signed-off-by:
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Wenjing Liu authored
[why] Remove the need to include dc_link.h separately. dc.h should contain everything needed on DM side. [How] Merge dc_link.h into dc.h and dc_types.h so DM only needs to include dc.h to use all link public functions. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Mustapha Ghaddar authored
[WHY & HOW] Update the declaration to give a better idea of what the function does. Reviewed-by:
Mustapha Ghaddar <mghaddar@amd.com> Tested-by:
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Aric Cyr authored
This reverts commit 6cfb6df2. [Why & How] Original change causes black screen. Revert until fix is available. Reviewed-by:
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Alvin Lee authored
[Why & How] - If for any reason PMFW fails to set the expected (or valid) DISPCLK WDIVIDER, then DAL will program DENTIST DISPCLK WDIVIDER to correct for this issue Reviewed-by:
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Sung Joon Kim authored
[why] More branch devices are able to support Freesync over PCon so include them in the list of supporting devices. [how] Add more compatible PCon devices in the whitelist for Freesync over Pcon. Reviewed-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
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Yihan Zhu authored
[WHY] DP 420 formats do not light up because the pixel processing mode of the DP_FORMAT is misprogrammed [HOW] Added appropriate programming for DP pixel format Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
Yihan Zhu <yihan.zhu@amd.com> Tested-by:
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Ayush Gupta authored
[Why] System restart observed while changing the display resolution to 8k with extended mode. Sytem restart was caused by a page fault. [How] When the driver populates subvp info it did it for both the pipes using vblank which caused an outof bounds array access causing the page fault. added checks to allow the top pipe only to fix this issue. Co-authored-by:
Ayush Gupta <ayush.gupta@amd.com> Reviewed-by:
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Hersen Wu authored
[why] during boot up or resume from s3, hw default value of domain_power_forceon is 1. when program domain_power_gate to 1 to power down hw block, hw will not change to power off due to domain_power_forceon = 1. [how] enable_power_gating_plane(true) should be executed to set domain_power_forceon to 0 before dsc_pg_control. dsc_pg_control is already called by dcn3x_init_hw--> init_pipes--> dsc_pg_control. no need be programmed with dcn3x_init_hw one more time. to trigger dchub, dsc block power state change, need program dc_ip_request_cntl to notify hw block. Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
Hersen Wu <hersenxs.wu@amd.com> Tested-by:
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Mustapha Ghaddar authored
[WHY & HOW] After we allocate BW at plug, we will de-alloc and allocate only what stream needs at stream_enable() [HOW] Introduce bw allocation check at link_enable() for DPIA links Reviewed-by:
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Aric Cyr authored
This reverts commit 4f1b5e73. [Why & How] Original change causes a regression. Revert until fix is available. Reviewed-by:
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Jasdeep Dhillon authored
[WHY] Adding 1920x1080 as fail safe mode for Video Format Fall Back Policy. Reviewed-by:
Jerry Zuo <Jerry.Zuo@amd.com> Acked-by:
Jasdeep Dhillon <jdhillon@amd.com> Tested-by:
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Aric Cyr authored
[WHY] udelay should not be used for long waits since it keeps CPU active, wasting power. [HOW] Use fsleep where acceptable to allow CPU cores to be parked by the scheduler. Reviewed-by:
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Alex Hung authored
[WHY] When PTEBufferSizeInRequests is zero, UBSAN reports the following warning because dml_log2 returns an unexpected negative value: shift exponent 4294966273 is too large for 32-bit type 'int' [HOW] In the case PTEBufferSizeInRequests is zero, skip the dml_log2() and assign the result directly. Reviewed-by:
Alex Hung <alex.hung@amd.com> Tested-by:
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Ryan Lin authored
[Why] Needs to set the default value of the LTTPR timeout after resume. [How] Set the default (3.2ms) timeout at resuming if the sink supports LTTPR Reviewed-by:
Ryan Lin <tsung-hua.lin@amd.com> Tested-by:
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Horatio Zhang authored
The call trace occurs when the amdgpu is removed after the mode1 reset. During mode1 reset, from suspend to resume, there is no need to reinitialize the ta firmware buffer which caused the bo pin_count increase redundantly. [ 489.885525] Call Trace: [ 489.885525] <TASK> [ 489.885526] amdttm_bo_put+0x34/0x50 [amdttm] [ 489.885529] amdgpu_bo_free_kernel+0xe8/0x130 [amdgpu] [ 489.885620] psp_free_shared_bufs+0xb7/0x150 [amdgpu] [ 489.885720] psp_hw_fini+0xce/0x170 [amdgpu] [ 489.885815] amdgpu_device_fini_hw+0x2ff/0x413 [amdgpu] [ 489.885960] ? blocking_notifier_chain_unregister+0x56/0xb0 [ 489.885962] amdgpu_driver_unload_kms+0x51/0x60 [amdgpu] [ 489.886049] amdgpu_pci_remove+0x5a/0x140 [amdgpu] [ 489.886132] ? __pm_runtime_resume+0x60/0x90 [ 489.886134] pci_device_remove+0x3e/0xb0 [ 489.886135] __device_release_driver+0x1ab/0x2a0 [ 489.886137] driver_detach+0xf3/0x140 [ 489.886138] bus_remove_driver+0x6c/0xf0 [ 489.886140] driver_unregister+0x31/0x60 [ 489.886141] pci_unregister_driver+0x40/0x90 [ 489.886142] amdgpu_exit+0x15/0x451 [amdgpu] Signed-off-by:
Horatio Zhang <Hongkun.Zhang@amd.com> Signed-off-by:
longlyao <Longlong.Yao@amd.com> Reviewed-by:
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Tom Rix authored
building with gcc and W=1 reports drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c:81:29: error: variable ‘ring’ set but not used [-Werror=unused-but-set-variable] 81 | struct amdgpu_ring *ring; | ^~~~ ring is not used so remove it. Signed-off-by:Tom Rix <trix@redhat.com> Signed-off-by:
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tiancyin authored
[Why] Variable adev->crtc_irq.num_types was initialized as the value of adev->mode_info.num_crtc at early_init stage, later at hw_init stage, the num_crtc changed due to the display pipe harvest on some SKUs, but the num_types was not updated accordingly, that cause below error in gpu recover. *ERROR* amdgpu_dm_set_crtc_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_crtc_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_crtc_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_pflip_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_pflip_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_pflip_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_pflip_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_vupdate_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_vupdate_irq_state: crtc is NULL at id :3 *ERROR* amdgpu_dm_set_vupdate_irq_state: crtc is NULL at id :3 [How] Defer the initialization of num_types to eliminate the error logs. Signed-off-by:
tiancyin <tianci.yin@amd.com> Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Mario Limonciello authored
A mistake has been made in the BIOS for some ASICs with NBIO 7.5.1 where some NBIO registers aren't properly setup. Ensure that they're set during initialization. Tested-by:
Richard Gong <richard.gong@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
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Harry Wentland authored
Format the input and output CSC matrix so they look like 3x4 matrixes. This will make parsing them much easier and allows us to quickly spot potential mistakes. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Harry Wentland authored
This will let us pass the kms_hdr.bpc_switch IGT test. The reason the bpc restriction was required is historical. At one point in time we were not falling back to a lower bpc when we didn't have enough bandwidth for the maximum bpc reported by a display. This meant that we couldn't enable some high refresh modes unless we limitted the bpc. Starting with this patch the issue is fixed: commit cbd14ae7 ("drm/amd/display: Fix incorrectly pruned modes with deep color") This patch implemented a fallback mechanism if mode validation failed at the max bpc. This means users now automatically get all modes that can be supported by at least 6 bpc. The driver will enable the mode with the highest possible bpc that is supported by the display. v2: - explain why this is no longer needed (Michel) - refer to commit that fixed bpc fallback (Michel) Signed-off-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Candice Li authored
Fixes following warnings: warning: no previous prototype for 'umc_v8_10_convert_error_address' warning: variable 'channel_index' set but not used Reported-by:
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- 23 Feb, 2023 2 commits
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Kun Liu authored
implement apu_thermal_cap r/w callback for vangogh Signed-off-by:
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Kun Liu authored
added a sysfs interface for thermal throttling, then userspace can get/update thermal limit Signed-off-by:
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