1. 19 Sep, 2014 9 commits
    • Marc Zyngier's avatar
      arm/arm64: KVM: vgic: switch to dynamic allocation · c1bfb577
      Marc Zyngier authored
      So far, all the VGIC data structures are statically defined by the
      *maximum* number of vcpus and interrupts it supports. It means that
      we always have to oversize it to cater for the worse case.
      
      Start by changing the data structures to be dynamically sizeable,
      and allocate them at runtime.
      
      The sizes are still very static though.
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      c1bfb577
    • Marc Zyngier's avatar
      KVM: ARM: vgic: plug irq injection race · 71afaba4
      Marc Zyngier authored
      As it stands, nothing prevents userspace from injecting an interrupt
      before the guest's GIC is actually initialized.
      
      This goes unnoticed so far (as everything is pretty much statically
      allocated), but ends up exploding in a spectacular way once we switch
      to a more dynamic allocation (the GIC data structure isn't there yet).
      
      The fix is to test for the "ready" flag in the VGIC distributor before
      trying to inject the interrupt. Note that in order to avoid breaking
      userspace, we have to ignore what is essentially an error.
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Acked-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      71afaba4
    • Christoffer Dall's avatar
      arm/arm64: KVM: vgic: Clarify and correct vgic documentation · 7e362919
      Christoffer Dall authored
      The VGIC virtual distributor implementation documentation was written a
      very long time ago, before the true nature of the beast had been
      partially absorbed into my bloodstream.  Clarify the docs.
      
      Plus, it fixes an actual bug.  ICFRn, pfff.
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      7e362919
    • Christoffer Dall's avatar
      arm/arm64: KVM: vgic: Fix SGI writes to GICD_I{CS}PENDR0 · 9da48b55
      Christoffer Dall authored
      Writes to GICD_ISPENDR0 and GICD_ICPENDR0 ignore all settings of the
      pending state for SGIs.  Make sure the implementation handles this
      correctly.
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      9da48b55
    • Christoffer Dall's avatar
      arm/arm64: KVM: vgic: Improve handling of GICD_I{CS}PENDRn · faa1b46c
      Christoffer Dall authored
      Writes to GICD_ISPENDRn and GICD_ICPENDRn are currently not handled
      correctly for level-triggered interrupts.  The spec states that for
      level-triggered interrupts, writes to the GICD_ISPENDRn activate the
      output of a flip-flop which is in turn or'ed with the actual input
      interrupt signal.  Correspondingly, writes to GICD_ICPENDRn simply
      deactivates the output of that flip-flop, but does not (of course) affect
      the external input signal.  Reads from GICC_IAR will also deactivate the
      flip-flop output.
      
      This requires us to track the state of the level-input separately from
      the state in the flip-flop.  We therefore introduce two new variables on
      the distributor struct to track these two states.  Astute readers may
      notice that this is introducing more state than required (because an OR
      of the two states gives you the pending state), but the remaining vgic
      code uses the pending bitmap for optimized operations to figure out, at
      the end of the day, if an interrupt is pending or not on the distributor
      side.  Refactoring the code to consider the two state variables all the
      places where we currently access the precomputed pending value, did not
      look pretty.
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      faa1b46c
    • Christoffer Dall's avatar
      arm/arm64: KVM: vgic: Clear queued flags on unqueue · cced50c9
      Christoffer Dall authored
      If we unqueue a level-triggered interrupt completely, and the LR does
      not stick around in the active state (and will therefore no longer
      generate a maintenance interrupt), then we should clear the queued flag
      so that the vgic can actually queue this level-triggered interrupt at a
      later time and deal with its pending state then.
      
      Note: This should actually be properly fixed to handle the active state
      on the distributor.
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      cced50c9
    • Christoffer Dall's avatar
      arm/arm64: KVM: Rename irq_active to irq_queued · dbf20f9d
      Christoffer Dall authored
      We have a special bitmap on the distributor struct to keep track of when
      level-triggered interrupts are queued on the list registers.  This was
      named irq_active, which is confusing, because the active state of an
      interrupt as per the GIC spec is a different thing, not specifically
      related to edge-triggered/level-triggered configurations but rather
      indicates an interrupt which has been ack'ed but not yet eoi'ed.
      
      Rename the bitmap and the corresponding accessor functions to irq_queued
      to clarify what this is actually used for.
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      dbf20f9d
    • Christoffer Dall's avatar
      arm/arm64: KVM: Rename irq_state to irq_pending · 227844f5
      Christoffer Dall authored
      The irq_state field on the distributor struct is ambiguous in its
      meaning; the comment says it's the level of the input put, but that
      doesn't make much sense for edge-triggered interrupts.  The code
      actually uses this state variable to check if the interrupt is in the
      pending state on the distributor so clarify the comment and rename the
      actual variable and accessor methods.
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      227844f5
    • Christoffer Dall's avatar
      Merge remote-tracking branch 'kvm/next' into queue · a875dafc
      Christoffer Dall authored
      Conflicts:
      	arch/arm64/include/asm/kvm_host.h
      	virt/kvm/arm/vgic.c
      a875dafc
  2. 17 Sep, 2014 6 commits
  3. 16 Sep, 2014 2 commits
    • Zhang Haoyu's avatar
      kvm: ioapic: conditionally delay irq delivery duringeoi broadcast · 184564ef
      Zhang Haoyu authored
      Currently, we call ioapic_service() immediately when we find the irq is still
      active during eoi broadcast. But for real hardware, there's some delay between
      the EOI writing and irq delivery.  If we do not emulate this behavior, and
      re-inject the interrupt immediately after the guest sends an EOI and re-enables
      interrupts, a guest might spend all its time in the ISR if it has a broken
      handler for a level-triggered interrupt.
      
      Such livelock actually happens with Windows guests when resuming from
      hibernation.
      
      As there's no way to recognize the broken handle from new raised ones, this patch
      delays an interrupt if 10.000 consecutive EOIs found that the interrupt was
      still high.  The guest can then make a little forward progress, until a proper
      IRQ handler is set or until some detection routine in the guest (such as
      Linux's note_interrupt()) recognizes the situation.
      
      Cc: Michael S. Tsirkin <mst@redhat.com>
      Signed-off-by: default avatarJason Wang <jasowang@redhat.com>
      Signed-off-by: default avatarZhang Haoyu <zhanghy@sangfor.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      184564ef
    • Guo Hui Liu's avatar
      KVM: x86: Use kvm_make_request when applicable · 105b21bb
      Guo Hui Liu authored
      This patch replace the set_bit method by kvm_make_request
      to make code more readable and consistent.
      Signed-off-by: default avatarGuo Hui Liu <liuguohui@gmail.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      105b21bb
  4. 11 Sep, 2014 5 commits
  5. 10 Sep, 2014 9 commits
  6. 05 Sep, 2014 5 commits
  7. 03 Sep, 2014 4 commits