- 08 Oct, 2018 40 commits
-
-
Aapo Vienamo authored
Set the default inbound timing adjustment tap value on reset and on non-tunable modes. The default tap value is not programmed on tunable modes because the tuning sequence is used instead to determine the tap value. Signed-off-by:
Aapo Vienamo <avienamo@nvidia.com> Acked-by:
Thierry Reding <treding@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
-
Aapo Vienamo authored
Parse the default inbound and outbound sampling trimmer values from the device tree. Signed-off-by:
-
Aapo Vienamo authored
Add quirk to disable the card clock during configuration of the tap value in tegra_sdhci_set_tap() and issue sdhci_reset() after value change. This is a workaround to avoid propagation of a potential glitch caused by setting the tap value. Signed-off-by:
-
Aapo Vienamo authored
Set NVQUIRK_HAS_PADCALIB on Tegra210 and Tegra186 to enable automatic pad drive strength calibration. Signed-off-by:
-
Aapo Vienamo authored
Run the automatic pad calibration after voltage switching if tegra_host->pad_calib_required is set. Signed-off-by:
-
Aapo Vienamo authored
Parse the pad drive strength calibration offsets from the device tree. Program the calibration offsets in accordance with the current signaling mode. Signed-off-by:
-
Aapo Vienamo authored
Disable the card clock during automatic pad drive strength calibration and re-enable it afterwards. Signed-off-by:
-
Aapo Vienamo authored
Automatic pad drive strength calibration is performed on a separate pad identical to the ones used for driving the actual bus. Power on the calibration pad during the calibration procedure and power it off afterwards to save power. Signed-off-by:
Mikko Perttunen <mperttunen@nvidia.com> Acked-by:
-
Aapo Vienamo authored
Configure the voltage reference used by the automatic pad drive strength calibration procedure. The value is a magic number from the TRM. Signed-off-by:
-
Aapo Vienamo authored
Implement polling with 10 ms timeout for automatic pad drive strength calibration. Signed-off-by:
-
Aapo Vienamo authored
Parse the pinctrl state and nvidia,only-1-8-v properties from the device tree. Validate the pinctrl and regulator configuration before unmasking UHS modes. Implement pad voltage state reconfiguration in the mmc start_signal_voltage_switch() callback. Add NVQUIRK_NEEDS_PAD_CONTROL and add set it for Tegra210 and Tegra186. The pad configuration is done in the mmc callback because the order of pad reconfiguration and sdhci voltage switch depend on the voltage to which the transition occurs. Signed-off-by:
-
Aapo Vienamo authored
Document the Tegra SDHCI inbound and outbound sampling trimmer values. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
-
Aapo Vienamo authored
Add bindings documentation for pad pull up and pull down offset values to be programmed before executing automatic pad drive strength calibration. Signed-off-by:
-
Aapo Vienamo authored
Document the pinctrl bindings used by the SDHCI driver to reconfigure pad voltages on controllers supporting multiple voltage levels. Signed-off-by:
-
Wolfram Sang authored
This variable is unused now after some refactoring. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
-
Wolfram Sang authored
Concise, but still readable. Signed-off-by:
-
Masaharu Hayakawa authored
SDR104, HS200 and HS400 need to check for SCC error. If SCC error is detected, retuning is necessary. Signed-off-by:
Masaharu Hayakawa <masaharu.hayakawa.ry@renesas.com> [Niklas: update commit message] Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by:
-
Masaharu Hayakawa authored
Checking for SCC error during retuning is unnecessary. Signed-off-by:
-
Niklas Söderlund authored
Add a helper to allow host drivers checking if a retune is in progress. Signed-off-by:
-
Masahiro Yamada authored
for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) clock <<= 1; ... is too tricky, hence I replaced with roundup_pow_of_two(divisor) >> 2 '(clk >> 22) & 0x1' is the bit test for the 1/1 divisor, but it is not clear. 'divisor <= 1' is easier to understand. Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by:
-
Masahiro Yamada authored
renesas_sdhi_clk_start() and renesas_sdhi_clk_stop() are now only called from renesas_sdhi_set_clock(). Merge them. Signed-off-by:
-
Jisheng Zhang authored
When using DMA, if the DMA addr spans 128MB boundary, we have to split the DMA transfer into two so that each one doesn't exceed the boundary. Signed-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by:
-
Jisheng Zhang authored
Add this hook so that it can be overridden with driver specific implementations. We also let the original sdhci_adma_write_desc() accept &desc so that the function can set its new value. Then export the function so that it could be reused by driver's specific implementations. Signed-off-by:
-
Jisheng Zhang authored
This patch adds adma_table_cnt member to struct sdhci_host to give more flexibility to drivers to control the ADMA table count. Default value of adma_table_cnt is set to (SDHCI_MAX_SEGS * 2 + 1). Signed-off-by:
-
Rob Herring authored
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Hu Ziji <huziji@marvell.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-mmc@vger.kernel.org Signed-off-by:
-
Aapo Vienamo authored
Allow SDHCI drivers to hook code before and after sdhci_request() by making it externally visible. Signed-off-by:
-
Wang Dongsheng authored
After host requests RESET_FOR_ALL action, the hardware output an interrupt for OS and waiting for the OS to approve. Before writing this fix, ACPI GED has handled the interrupt. But the ACPI GED belongs to a slow process, and sometimes the handling process time is more than 100ms(Mutex wait more than 100ms). So drop the GED solution and add this quirk fix. Signed-off-by:
Wang Dongsheng <dongsheng.wang@hxt-semitech.com> Acked-by:
-
Wang Dongsheng authored
The device specific resource can be free in free_slot after removing host controller. Signed-off-by:
-
Yinbo Zhu authored
In tuning mode of operation, when TBCTL[TB_EN] is set, eSDHC may report one of the following errors : 1)Tuning error while running tuning operation where SYSCTL2[SAMPCLKSEL] will not get set even when SYSCTL2[EXTN] is reset. OR 2)Data transaction error (e.g. IRQSTAT[DCE], IRQSTAT[DEBE]) during data transaction errors. This issue occurs when the data window sampled within eSDHC is in full cycle. So, in that case, eSDHC is not able to find out the start and end points of the data window and sets the sampling pointer at default location (which is middle of the internal SD clock). If this sampling point coincides with the data eye boundary, then it can result in the above mentioned errors. Impact: Tuning mode of operation for SDR50, SDR104 or HS200 speed modes may not work properly Workaround: In case eSDHC reports tuning error or data errors in tuning mode of operation, by add the erratum A008171 support to fix the issue. Signed-off-by:
Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by:
-
Yinbo Zhu authored
This patch is to add tuning error codes to judge tuning state Signed-off-by:
-
Masahiro Yamada authored
Here is another TMIO MMC variant found in Socionext UniPhier SoCs. As commit b6147490 ("mmc: tmio: split core functionality, DMA and MFD glue") said, these MMC controllers use the IP from Panasonic. However, the MMC controller in the TMIO (Toshiba Mobile IO) MFD chip was the first upstreamed user of this IP. The common driver code for this IP is now called 'tmio-mmc-core' in Linux although it is a historical misnomer. Anyway, this driver select's MMC_TMIO_CORE to borrow the common code from tmio-mmc-core.c Older UniPhier SoCs (LD4, Pro4, sLD8) support the external DMA engine like renesas_sdhi_sys_dmac.c. The difference is UniPhier SoCs use a single DMA channel whereas Renesas chips request separate channels for RX and TX. Newer UniPhier SoCs (Pro5 and later) support the internal DMA engine like renesas_sdhi_internal_dmac.c The register map is almost the same, so I guess Renesas and Socionext use the same internal DMA hardware. The main difference is, the register offsets are doubled for Renesas. Renesas Socionext SDHI UniPhier DM_CM_DTRAN_MODE 0x820 0x410 DM_CM_DTRAN_CTRL 0x828 0x414 DM_CM_RST 0x830 0x418 DM_CM_INFO1 0x840 0x420 DM_CM_INFO1_MASK 0x848 0x424 DM_CM_INFO2 0x850 0x428 DM_CM_INFO2_MASK 0x858 0x42c DM_DTRAN_ADDR 0x880 0x440 DM_DTRAN_ADDREX --- 0x444 This comes from the difference of host->bus_shift; 2 for Renesas SoCs, and 1 for UniPhier SoCs. Also, the datasheet for UniPhier SoCs defines DM_DTRAN_ADDR and DM_DTRAN_ADDREX as two separate registers. It could be possible to factor out the DMA common code by introducing some hooks to cope with platform quirks, but this patch does not touch that for now. Signed-off-by:
-
Masahiro Yamada authored
This SD/eMMC controller is used for UniPhier SoC family. Signed-off-by:
-
Masahiro Yamada authored
tmio_mmc_set_clock() is full of quirks because different SoC vendors extended this in different ways. The original IP defines the divisor range 1/2 ... 1/512. bit 7 is set: 1/512 bit 6 is set: 1/256 ... bit 0 is set: 1/4 all bits clear: 1/2 It is platform-dependent how to achieve the 1/1 clock. I guess the TMIO-MFD variant uses the clock selector outside of this IP, as far as I see tmio_core_mmc_clk_div() in drivers/mfd/tmio_core.c I guess bit[7:0]=0xff is Renesas-specific extension. Socionext (and Panasonic) uses bit 10 (CLKSEL) for 1/1. Also, newer versions of UniPhier SoC variants use bit 16 for 1/1024. host->clk_update() is only used by the Renesas variants, whereas host->set_clk_div() is only used by the TMIO-MFD variants. To cope with this mess, promote tmio_mmc_set_clock() to a new platform hook ->set_clock(), and melt the old two hooks into it. Signed-off-by:
-
Masahiro Yamada authored
tmio_mmc_clk_stop(host) is equivalent to tmio_mmc_set_clock(host, 0). This replacement is needed for the next commit. Signed-off-by:
-
Paul Cercueil authored
The JZ4725B is the first JZ SoC version that introduced a 32-bit IMASK register, not the JZ4750. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Signed-off-by:
-
Wolfram Sang authored
Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
-
Sergei Shtylyov authored
Document the R-Car V3M (R8A77970) SoC in the R-Car SDHI bindings -- it's the usual R-Car gen3 compatible controller with the internal DMA engine. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
-
Sergei Shtylyov authored
I've successfully tested eMMC on the V3H Starter Kit board and since the R8A77970 SoC has a single SDHI core, it can't be a subject to the known RX DMA errata. Signed-off-by:
-
Sergei Shtylyov authored
Remove the stray underscore in the DM_CM_DTRAN_MODE.BUS_WIDTH register field name and fix the typo in the comment of the #define DTRAN_MODE_CH_NUM_CH1. Signed-off-by:
-
Paul Cercueil authored
Depending on MACH_JZ4740 | MACH_JZ4780 prevent us from creating a generic kernel that works on more than one MIPS board. Instead, we just depend on MIPS being set. Signed-off-by:
-
