- 09 Oct, 2020 2 commits
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Christian Hewitt authored
Amlogic SoC devices report the following errors frequently causing excessive dmesg log spam and early log rotataion, although the errors appear to be harmless as everything works fine: [ 7.202702] panfrost ffe40000.gpu: error powering up gpu L2 [ 7.203760] panfrost ffe40000.gpu: error powering up gpu shader ARM staff have advised increasing the timeout values to eliminate the errors in most normal scenarios, and testing with several different G31/G52 devices shows 20000 to be a reliable value. Fixes: f3ba9122 ("drm/panfrost: Add initial panfrost driver") Suggested-by:
Steven Price <steven.price@arm.com> Signed-off-by:
Christian Hewitt <christianshewitt@gmail.com> Reviewed-by:
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Ondrej Jirman authored
The driver was renamed, change the path in the MAINTAINERS file. Signed-off-by:
Ondrej Jirman <megous@megous.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://lore.kernel.org/lkml/20200701184640.1674969-1-megous@megous.com/#t
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- 07 Oct, 2020 1 commit
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Paul Cercueil authored
This reverts commit 37054fc8 ("gpu/drm: ingenic: Add option to mmap GEM buffers cached") At the very moment this commit was created, the DMA API it relied on was modified in the DMA tree, which caused the driver to break in linux-next. Revert it for now, and it will be resubmitted later to work with the new DMA API. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Acked-by:
Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20201004141758.1013317-1-paul@crapouillou.net
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- 25 Sep, 2020 2 commits
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Maxime Ripard authored
The HVS FIFOs are currently assigned each time we have an atomic_check for all the enabled CRTCs. However, if we are running multiple outputs in parallel and we happen to disable the first (by index) CRTC, we end up changing the assigned FIFO of the second CRTC without disabling and reenabling the pixelvalve which ends up in a stall and eventually a VBLANK timeout. In order to fix this, we can create a special value for our assigned channel to mark it as disabled, and if our CRTC already had an assigned channel in its previous state, we keep on using it. Fixes: 87ebcd42 ("drm/vc4: crtc: Assign output to channel automatically") Signed-off-by:
Maxime Ripard <maxime@cerno.tech> Tested-by:
Dave Stevenson <dave.stevenson@raspberrypi.com> Reviewed-by:
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Maxime Ripard authored
The current CRTC state reset hook in vc4 allocates a vc4_crtc_state structure as a drm_crtc_state, and relies on the fact that vc4_crtc_state embeds drm_crtc_state as its first member, and therefore can be safely cast. However, this is pretty fragile especially since there's no check for this in place, and we're going to need to access vc4_crtc_state member at reset so this looks like a good occasion to make it more robust. Fixes: 6d6e5003 ("drm/vc4: Allocate the right amount of space for boot-time CRTC state.") Signed-off-by:
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- 23 Sep, 2020 1 commit
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Maxime Ripard authored
The HVS has three FIFOs that can be assigned to a number of PixelValves through a mux. However, changing that FIFO requires that we disable and then enable the pixelvalve, so we want to assign FIFOs to all the enabled CRTCs, and not just the active ones. Fixes: 87ebcd42 ("drm/vc4: crtc: Assign output to channel automatically") Signed-off-by:
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- 21 Sep, 2020 9 commits
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Maxime Ripard authored
The vc4 display engine has a first controller called the HVS that will perform the composition of the planes. That HVS has 3 FIFOs and can therefore compose planes for up to three outputs. The timings part is generated through a component called the Pixel Valve, and the BCM2711 has 6 of them. Thus, the HVS has some bits to control which FIFO gets output to which Pixel Valve. The current code supports that muxing by looking at all the CRTCs in a new DRM atomic state in atomic_check, and given the set of constraints that we have, assigns FIFOs to CRTCs or reject the mode entirely. The actual muxing will occur during atomic_commit. However, that doesn't work if only a fraction of the CRTCs' state is updated in that state, since it will ignore the CRTCs that are kept running unmodified, and will thus unassign its associated FIFO, and later disable it. In order to make the code work as expected, let's pull the CRTC state of all the enabled CRTC in our atomic_check so that we can operate on all the running CRTCs, no matter whether they are affected by the new state or not. Fixes: 87ebcd42 ("drm/vc4: crtc: Assign output to channel automatically") Signed-off-by:
Hoegeun Kwon <hoegeun.kwon@samsung.com> Tested-by:
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Tian Tao authored
Update kernel-doc line comments to fix warnings reported by make W=1. drivers/gpu/drm/ttm/ttm_memory.c:271: warning: Function parameter or member 'glob' not described in 'ttm_shrink' drivers/gpu/drm/ttm/ttm_memory.c:271: warning: Function parameter or member 'from_wq' not described in 'ttm_shrink' drivers/gpu/drm/ttm/ttm_memory.c:271: warning: Function parameter or member 'extra' not described in 'ttm_shrink' drivers/gpu/drm/ttm/ttm_memory.c:271: warning: Function parameter or member 'ctx' not described in 'ttm_shrink' Signed-off-by:
Tian Tao <tiantao6@hisilicon.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Link: https://patchwork.freedesktop.org/patch/391317/Signed-off-by:
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Neil Armstrong authored
This adds the required GPU quirks, including the quirk in the PWR registers at the GPU reset time and the IOMMU quirk for shareability issues observed on G52 in Amlogic G12B SoCs. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Signed-off-by:
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Neil Armstrong authored
The T820, G31 & G52 GPUs integrated by Amlogic in the respective GXM, G12A/SM1 & G12B SoCs needs a quirk in the PWR registers at the GPU reset time. Since the Amlogic's integration of the GPU cores with the SoC is not publicly documented we do not know what does these values, but they permit having a fully functional GPU running with Panfrost. Signed-off-by:
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Neil Armstrong authored
The T820, G31 & G52 GPUs integrated by Amlogic in the respective GXM, G12A/SM1 & G12B SoCs needs a quirk in the PWR registers after each reset. This adds a callback in the device compatible struct of permit this. Signed-off-by:
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Daniel Vetter authored
We can now also delete drm_dev_init, now that vkms, vgem and i915 selftests are resolved. Reviewed-by:
Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by:
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Luben Tuikov authored
Convert to using devm_drm_dev_alloc(), as drm_dev_init() is going away. v2: Remove drm_dev_put() since a) devres doesn't do refcounting, see Documentation/driver-api/driver-model/devres.rst, Section 4, paragraph 1; and since b) devres acts as garbage collector when the DRM device's parent's devres "action" callback is called to free the container device (amdgpu_device), which embeds the DRM dev. Acked-by:Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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Daniel Vetter authored
To avoid having to create all the device and driver scaffolding we just manually create and destroy a devres_group. v2: Rebased v3: use devres_open/release_group so we can use devm without real hacks in the driver core or having to create an entire fake bus for testing drivers. Might want to extract this into helpers eventually, maybe as a mock_drm_dev_alloc or test_drm_dev_alloc. v4: - Fix IS_ERR handling (Matt) - Delete surplus put_device() in mock_device_release (intel-gfx-ci) v5: - do not switch to device_add - it breaks runtime pm in the tests and with the devres_group_add/release no longer needed for automatic cleanup (CI). Update commit message to match. - print correct error in pr_err (Matt) v6: Remove now unused err variable (CI). v7: More warning fixes ... Acked-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Matthew Auld <matthew.william.auld@gmail.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> (v3) Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matthew Auld <matthew.william.auld@gmail.com> (v4) Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200919134032.2488403-1-daniel.vetter@ffwll.ch
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Daniel Vetter authored
Just some prep work before we rework the lifetime handling, which requires replacing all the drm_dev_put in selftests by something else. v2: Don't go with a static inline, upsets the header tests and separation. Acked-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
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- 18 Sep, 2020 2 commits
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Jing Xiangfeng authored
Remove the superfluous break, as there is a 'return' before it. Fixes: bad07ff7 ("fbcon: smart blitter usage for scrolling") Signed-off-by:
Jing Xiangfeng <jingxiangfeng@huawei.com> Reviewed-by:
Nick Desaulniers <ndesaulniers@google.com> Reviewed-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by:
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Vaibhav Gupta authored
The changes made in below mentioned commit removed CONFIG_PM containers from drivers/video/fbdev/aty/atyfb_base.c but not from drivers/video/fbdev/aty/atyfb.h for respective callbacks. This resulted in error for implicit declaration for those callbacks. Fixes: 348b2956 ("fbdev: aty: use generic power management") Signed-off-by:
Vaibhav Gupta <vaibhavgupta40@gmail.com> Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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- 17 Sep, 2020 14 commits
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Dave Airlie authored
This was unused. Signed-off-by:
Dave Airlie <airlied@redhat.com> Reviewed-by:
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Dave Airlie authored
The two accel cleanup paths were mostly the same once refactored. Just pass a bool to say if the evictions are to be pipelined. Signed-off-by:
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Dave Airlie authored
The pipeline and accel cleansups has similiar paths here. Signed-off-by:
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Dave Airlie authored
Both accel cleanup and pipeline move had the same code, make a single function for it. Signed-off-by:
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Dave Airlie authored
This pattern is called in a few places, just clean it up. Reviewed-by:
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Dave Airlie authored
Now the bind functions have all the protection explicitly the drivers can just call them directly, and the api can be unexported Reviewed-by:
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Dave Airlie authored
This moves unbind into the driver side on destroy paths. Reviewed-by:
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Dave Airlie authored
Call the driver first and have it call the common code cleanup. This is useful later to fix unbind. Reviewed-by:
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Dave Airlie authored
This moves the generic tracking into the drivers and protects against reentrancy in the drivers. It fixes up radeon and agp to be able to query the bound status as that is required. Reviewed-by:
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Christian König authored
Extern is the default attribute for functions anyway. Signed-off-by:
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Daniel Vetter authored
GPU drivers need this in their shrinkers, to be able to throw out mmap'ed buffers. Note that we also need dma_resv_lock in shrinkers, but that loop is resolved by trylocking in shrinkers. So full hierarchy is now (ignore some of the other branches we already have primed): mmap_read_lock -> dma_resv -> shrinkers -> i_mmap_lock_write I hope that's not inconsistent with anything mm or fs does, adding relevant people. Reviewed-by:
Thomas Hellström <thomas.hellstrom@intel.com> Reviewed-by:
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Wang Qing authored
Change the comment typo: "manger" -> "manager". Signed-off-by:
Wang Qing <wangqing@vivo.com> Signed-off-by:
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Lukas Bulwahn authored
Commit f15a3ea8 ("MAINTAINERS: Add ASPEED BMC GFX DRM driver entry") does not mention that linux-aspeed@lists.ozlabs.org is moderated for non-subscribers, but the other three entries for linux-aspeed@lists.ozlabs.org do. By 'majority vote' among entries, let us assume it was just missed here and adjust it to be consistent with others. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Signed-off-by:
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Christian König authored
Unexport ttm_check_under_lowerlimit. Make ttm_bo_acc_size static and unexport it. Remove ttm_get_kernel_zone_memory_size. Signed-off-by:
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- 16 Sep, 2020 8 commits
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Maxime Ripard authored
Merge branch 'virtio-shm' of git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/fuse into drm-misc-next Topic pull request for core virtio changes that will be required by the DRM driver. Signed-off-by:
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Thomas Zimmermann authored
An active cursor plane requires a valid display mode. Change the commit_tail callback, so that it sets up the CRTC's mode before updating planes. Signed-off-by:
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Thomas Zimmermann authored
This change simplifies ast's modesetting code. The display mode is now programmed from within the CRTC's atomic_enable(), which only runs if we actually want to program the mode. Corresponding code in atomic_flush() is being removed. Also removed is atomic_begin(), which serves no purpose at all. Signed-off-by:
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Thomas Zimmermann authored
The ast HW cursor requires the primary plane and CRTC to display at a valid mode and format. This is not the case while switching display modes, which can lead to the screen turing permanently dark. As a workaround, the ast driver now disables active planes while the mode or format switch takes place. It also synchronizes with the vertical refresh to give CRTC and planes some time to catch up on each other. The active planes planes (primary or cursor) will be re-enabled by each plane's atomic_update() function. v3: * move the logic into the CRTC's atomic_disable function v2: * move the logic into the commit-tail function Signed-off-by:
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Thomas Zimmermann authored
The atomic modesetting code tried to distinguish format changes from full modesetting operations. But the implementation was buggy and the format registers were often updated even for simple pageflips. Fix this problem by handling format changes in the primary plane's update function. v3: * program format in primary plane's update function Signed-off-by:
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Thomas Zimmermann authored
I'm adding myself as reviewer for ast, mgag200 and udl. I've already been keeping these drivers in shape for a while. While at it I'm also setting the list and tree for ast and mgag200, and update each driver's status to Supported. Working on these drivers is part of my job. Signed-off-by:
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Stefan Agner authored
The lcdif IP does not support a framebuffer pitch (stride) other than framebuffer width. Check for equality and reject the framebuffer otherwise. This prevents a distorted picture when using 640x800 and running the Mesa graphics stack. Mesa tries to use a cache aligned stride, which leads at that particular resolution to width != stride. Currently Mesa has no fallback behavior, but rejecting this configuration allows userspace to handle the issue correctly. Fixes: 45d59d70 ("drm: Add new driver for MXSFB controller") Signed-off-by:
Stefan Agner <stefan@agner.ch> Reviewed-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200908141654.266836-1-stefan@agner.ch
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Tian Tao authored
Handing the return value of drm_universal_plane_init to fix the following W=1 kernel build warning(s): vc4_plane.c: In function ‘vc4_plane_init’: vc4_plane.c:1340:6: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable] Signed-off-by:
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- 15 Sep, 2020 1 commit
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Dave Airlie authored
Just use the top bit of page flags to store the populated state. Reviewed-by:
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