1. 17 May, 2006 1 commit
    • Dimitry Andric's avatar
      [ARM] 3529/1: s3c24xx: fix restoring control register with undefined instruction · c3fb0416
      Dimitry Andric authored
      Patch from Dimitry Andric
      
      In arch/arm/mach-s3c2410/sleep.S, the coprocessor registers are saved at
      suspend time, and restored at resume time. However, an undefined
      instruction is used when attempting to restore a non-existent "auxiliary
      control register".  This leads to a crash on S3C2412, which has an ARM926
      core instead of an ARM920.
      
      At suspend time, the following fragment runs:
      
      	mrc	p15, 0, r7, c2, c0, 0	@ translation table base address
      	mrc	p15, 0, r8, c2, c0, 0	@ auxiliary control register
      	mrc	p15, 0, r9, c1, c0, 0	@ control register
      
      and at resume time, the following fragment runs:
      
      	mcr	p15, 0, r7, c2, c0, 0		@ translation table base
      	mcr	p15, 0, r8, c1, c1, 0		@ auxilliary control
      	...
      	mcr	p15, 0, r9, c1, c0, 0		@ turn on MMU, etc
      
      There are several problems with these fragments:
      1. The ARM920 and ARM926 cores don't have any "auxiliary control
         register", at least not according to the ARM920 and ARM926 TRM's.
      2. The 2nd line of suspend erroneously saves the c2 register again.
      3. This saved c2 value is restored using an undefined instruction.  For
         some reason this does not crash on ARM920, but does crash on ARM926.
      
      The following patch fixes all these problems.
      Signed-off-by: default avatarDimitry Andric <dimitry@andric.com>
      Yes, this looks sensible
      Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
      Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      c3fb0416
  2. 16 May, 2006 29 commits
  3. 15 May, 2006 10 commits