- 18 Jul, 2019 40 commits
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Eric Yang authored
[Why] Seamless boot optimization removed proper front end power off sequence. In driver disable enable case, this causes driver to power gate hubp and dpp while there is still memory fetching going on, this can cause invalid memory requests to be generated which will hang data fabric. [How] Put back proper front end power off sequence Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nikola Cornij authored
[why] Right now we FEC_READY is set only before the final link training, i.e. at mode set time. This means FEC_READY won't be set when doing link training as a response to HPD. It also fails UCD400 FEC test in DP compliance. [how] Move FEC_READY setup to link training. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by:
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Eric Bernstein authored
Use helper to determine if HDMI signal when processing avmute. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Murton Liu authored
[Why] Logic & structures for generic regs does not exist in DC currently. [How] Implement register masks/shifts and relevant functions for generic mux, similar to existing HPD and DDC objects. V2: fix includes for kalloc/free (Alex) Signed-off-by:
Murton Liu <murton.liu@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
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Alvin Lee authored
[why] In pipe split issue occurs when we program immediate flip while vsync flip is pending [how] Don't program immediate flip until flip is no longer pending Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Jaehyun Chung <Jaehyun.Chung@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Fatemeh Darbehani authored
[Why] Some display's hsync width is lower than the minimum dcn20 is set to support right now. This will cause optc1_validate_timing to fail which eventually will result in wrong set mode. This was set to 8 as per HW team's request for no valid reason. [How] Changing min_h_sync_width to 4 will let us validate timing for preffered mode and light up the headset. This change was made to Vega 10 before for a similar issue. Signed-off-by:
Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by:
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Alvin Lee authored
[why] We initialize pp_smu twice [how] Remove second initialization of pp_smu Signed-off-by:
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Su Sung Chung authored
[why] dcn20_clk_mgr_construct was not initializing pp_smu, and PME call gets filtered out by the null check [how] initialize pp_smu dcn20_clk_mgr_construct Signed-off-by:
Su Sung Chung <Su.Chung@amd.com> Reviewed-by:
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Tai Man authored
[Why] On some platforms, the encoder id 3 is not populated. So the encoders are not stored in right order as index (id: 0, 1, 2, 4, 5) at pool. This would cause encoders id 4 & id 5 to fail when finding corresponding audio device, defaulting to the first available audio device. As result, we cannot stream audio into two DP ports with encoders id 4 & id 5. [How] It need to create enough audio device objects (0 - 5) to perform matching. Then use encoder engine id to find matched audio device. Signed-off-by:
Tai Man <taiman.wong@amd.com> Reviewed-by:
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Harry Wentland authored
[Why] link_stream is never NULL here as we've dereferenced it a couple lines before and have done so for a couple months now. [How] - Drop the NULL check. - Initialize where we know link_stream is non-NULL Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Charlene Liu authored
[Description] Do not fill Null packet in the blank period for new packet gen This is based on HW IP team recommended default setting change. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Zi Yu Liao authored
[why] When the system is going into suspend, set_backlight gets called after the eDP got blanked. Since smooth brightness is enabled, the driver will make a call into the DMCU to ramp the brightness. The DMCU would try to enable ABM to do so. But since the display is blanked, this ends up causing ABM1_ACE_DBUF_REG_UPDATE_PENDING to get stuck at 1, which results in a dead lock in the DMCU firmware. [how] Disable brightness ramping when the eDP display is blanked. Signed-off-by:
Zi Yu Liao <ziyu.liao@amd.com> Reviewed-by:
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Alvin Lee authored
[Why] When we recover from hang, we do not want to skip the audio enable call. [How] Disable audio in dc_reinitialize_hardware Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Nikola Cornij authored
[why] DSC should be powered-on only on as-needed basis, i.e. if the mode requires it [how] Loop over all the DSCs at driver init time and power-gate each Signed-off-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Current default is sufficient for a flag that does not change. Signed-off-by:
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Derek Lai authored
[Why] When launch D10.2, driver will write DPCD 0x107 with 0x00 [How] Read MAX_DOWNSPREAD (0x0003h) then keep in current link settings Signed-off-by:
Derek Lai <Derek.Lai@amd.com> Reviewed-by:
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Ilya Bakoulin authored
[Why] A hubp pointer was being passed to DCN1 functions, which expect the enclosing structure (for the purpose of container_of macros) to be dcn10_hubp, but the actual type was dcn20_hubp. [How] Copy existing DCN1 functions and alter them slightly for use with dcn20_hubp. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
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Ilya Bakoulin authored
Before accessing it's vtable, check that stream_encoder is non-null. Signed-off-by:
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Ilya Bakoulin authored
[Why] Need to implement register programming for HDR dynamic metadata transmission and tests. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
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SivapiriyanKumarasamy authored
[WHY] Currently we don't wait for blacklight programming completion in DMCU when setting backlight level. Some sequences such as PSR static screen event trigger reprogramming requires it to be complete. [How] Add generic wait for dmcu command completion in set backlight level. Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
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Dingchen Zhang authored
[Why] We need to check the pipe crc source through debugfs for bypass mode test. [How] add implementation of amdgpu_dm_crtc_get_crc_sources and hook into drm_crtc callback get_crc_sources. Signed-off-by:
Dingchen Zhang <dingchen.zhang@amd.com> Reviewed-by:
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Dingchen Zhang authored
[Why] We need to compare DPRX CRCs with framebuffer CRCs for digital bypass mode. [How] Hook into DRM to grab DP receiver CRCs through drm_dp_start_crc. Signed-off-by:
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Julian Parkin authored
[Why] Hardware docs state that we must wait until the GPUVM context is ready after programming it. [How] Poll until the valid bit of PAGE_TABLE_BASE_ADDR_LO32 is set to 1 after programming it. v2: fix include for udelay (Alex) Signed-off-by:
Julian Parkin <julian.parkin@amd.com> Reviewed-by:
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Anthony Koo authored
[Why] Specifically to one panel, TCON is able to accept active video signal quickly, but the Source Driver requires 2-3 frames of extra time. It is a Panel issue since TCON needs to take care of all Sink requirements including Source Driver. But in this case it does not. Customer is asking to add fixed T7 delay as panel workaround. [How] Add monitor specific patch to add T7 delay Signed-off-by:
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Dmytro Laktyushkin authored
This change adds EMP packet programming for enabling dsc with hdmi. The packets are structured according to VESA HDMI 2.1x r2 spec, section 10.10.2.2. Signed-off-by:
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Su Sung Chung authored
[why] for 2 purposes: 1. get raw register value dumped on the log, which will make it easier to talk to other team who only knows about the register 2. enable other HW to be able to use the same interface as raven to log clock register data Signed-off-by:
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Wenjing Liu authored
[why] The current code will not wait for the entire frame after global unlock. This causes dsc dynamic target bpp update corruption when there is a surface update immediately happens after this. [how] Wait for the entire whole frame after unlock before continuing the rest of stream and surface update. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Nevenko Stupar authored
[Why] -Pass and use pixel clock in 100 Hz to Audio for HDMI audio DTO for Audio wall clock programming so audio DTO gets increased precision for timings with /1001 factor. -For HDMI TMDS for N and CTS ACR tables are based on 10 KHz units, these does not need to be modified as N and CTS values are still valid using current tables. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] For DCE110, DCE112 and DCE120 the max_clks_by_state for the clk_mgr are copied from their respective table before the call to dce_clk_mgr_construct, but then dce_clk_mgr_construct overwrites these with the dce80_max_clks_by_state. [How] Copy these after we call dce_clk_mgr_construct so we're using the right tables. Signed-off-by:
David Francis <David.Francis@amd.com> Acked-by:
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Murton Liu authored
[why] We reset the optimized_required in atomic_plane_disable flag immediately after it is set in atomic_plane_disconnect, causing us to never have flag set during next flip in UpdatePlanes. [how] Optimize directly after each time plane is removed. Signed-off-by:
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David Galiffi authored
[WHY] TRAINING_AUX_RD_INTERVAL (DPCD 000Eh) modifies the read interval for the EQ training sequence. CR read interval should remain 100 us. Currently, the CR interval is also being modified. [HOW] lt_settings->cr_pattern_time should always be 100 us. Signed-off-by:
David Galiffi <david.galiffi@amd.com> Reviewed-by:
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Aric Cyr authored
Signed-off-by:
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Charlene Liu authored
There are shared regs and code across DCN generations. Pull them out into a shared common location. Also, expose some dcn20 init functions. Signed-off-by:
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Samson Tam authored
[Why] Fixes issue when we have a display connected using a passive dongle and then emulate over it using a DP connection at 1 x 1.62 Ghz. System hangs because register bus returns back 0xFFFFFFFF for all register reads after setting register DIG_BE_CNTL in dcn10_link_encoder_connect_dig_be_to_fe(). Hang occurs later when trying to do a register read. [How] At the start of the emulation, dc_link_set_preferred_link_settings() and dp_retrain_link_dp_test() is called, even though it is connected using a passive dongle. Add an extra condition in dp_retrain_link_dp_test() to check for link->dongle_max_pix_clk > 0. This is the only way we know if the connection is using passive dongle so we don't retrain DP. Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
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Jun Lei authored
[why] Currently logical values are swapped in HW, causing system aperture to be undefined, so VA and PA cannot co-exist [how] program values correctly Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Nikola Cornij authored
[why] 'second_line_offset_adj' was mistakenly left at zero, even though DSC spec v1.2a recommends setting this field to 512 for 4:2:0. [how] Set 'second_line_offset_adj' to 512 for 4:2:0 and leave at zero otherwise Signed-off-by:
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Dmytro Laktyushkin authored
We're not expected to enter the default case, but not returning a default value here is incorrect. Signed-off-by:
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Eric Yang authored
[Why] Unintentionally introduced behaviour change from previous refactor, which causes clks to be 0 in no stream cases, which will cause divide by 0. [How] Skip calculation of clocks when no stream. Which is the same as old behaviour. Signed-off-by:
Tony Cheng <tong.cheng@amd.com> Acked-by:
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