1. 04 Feb, 2015 1 commit
    • James Hogan's avatar
      KVM: MIPS: Disable HTW while in guest · c4c6f2ca
      James Hogan authored
      Ensure any hardware page table walker (HTW) is disabled while in KVM
      guest mode, as KVM doesn't yet set up hardware page table walking for
      guest mappings so the wrong mappings would get loaded, resulting in the
      guest hanging or crashing once it reaches userland.
      
      The HTW is disabled and re-enabled around the call to
      __kvm_mips_vcpu_run() which does the initial switch into guest mode and
      the final switch out of guest context. Additionally it is enabled for
      the duration of guest exits (i.e. kvm_mips_handle_exit()), getting
      disabled again before returning back to guest or host.
      
      In all cases the HTW is only disabled in normal kernel mode while
      interrupts are disabled, so that the HTW doesn't get left disabled if
      the process is preempted.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Markos Chandras <markos.chandras@imgtec.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: kvm@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org> # v3.17+
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      c4c6f2ca
  2. 03 Feb, 2015 6 commits
    • Wincy Van's avatar
      KVM: nVMX: Enable nested posted interrupt processing · 705699a1
      Wincy Van authored
      If vcpu has a interrupt in vmx non-root mode, injecting that interrupt
      requires a vmexit.  With posted interrupt processing, the vmexit
      is not needed, and interrupts are fully taken care of by hardware.
      In nested vmx, this feature avoids much more vmexits than non-nested vmx.
      
      When L1 asks L0 to deliver L1's posted interrupt vector, and the target
      VCPU is in non-root mode, we use a physical ipi to deliver POSTED_INTR_NV
      to the target vCPU.  Using POSTED_INTR_NV avoids unexpected interrupts
      if a concurrent vmexit happens and L1's vector is different with L0's.
      The IPI triggers posted interrupt processing in the target physical CPU.
      
      In case the target vCPU was not in guest mode, complete the posted
      interrupt delivery on the next entry to L2.
      Signed-off-by: default avatarWincy Van <fanwenyi0529@gmail.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      705699a1
    • Wincy Van's avatar
      KVM: nVMX: Enable nested virtual interrupt delivery · 608406e2
      Wincy Van authored
      With virtual interrupt delivery, the hardware lets KVM use a more
      efficient mechanism for interrupt injection. This is an important feature
      for nested VMX, because it reduces vmexits substantially and they are
      much more expensive with nested virtualization.  This is especially
      important for throughput-bound scenarios.
      Signed-off-by: default avatarWincy Van <fanwenyi0529@gmail.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      608406e2
    • Wincy Van's avatar
      KVM: nVMX: Enable nested apic register virtualization · 82f0dd4b
      Wincy Van authored
      We can reduce apic register virtualization cost with this feature,
      it is also a requirement for virtual interrupt delivery and posted
      interrupt processing.
      Signed-off-by: default avatarWincy Van <fanwenyi0529@gmail.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      82f0dd4b
    • Wincy Van's avatar
      KVM: nVMX: Make nested control MSRs per-cpu · b9c237bb
      Wincy Van authored
      To enable nested apicv support, we need per-cpu vmx
      control MSRs:
        1. If in-kernel irqchip is enabled, we can enable nested
           posted interrupt, we should set posted intr bit in
           the nested_vmx_pinbased_ctls_high.
        2. If in-kernel irqchip is disabled, we can not enable
           nested posted interrupt, the posted intr bit
           in the nested_vmx_pinbased_ctls_high will be cleared.
      
      Since there would be different settings about in-kernel
      irqchip between VMs, different nested control MSRs
      are needed.
      Signed-off-by: default avatarWincy Van <fanwenyi0529@gmail.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      b9c237bb
    • Wincy Van's avatar
      KVM: nVMX: Enable nested virtualize x2apic mode · f2b93280
      Wincy Van authored
      When L2 is using x2apic, we can use virtualize x2apic mode to
      gain higher performance, especially in apicv case.
      
      This patch also introduces nested_vmx_check_apicv_controls
      for the nested apicv patches.
      Signed-off-by: default avatarWincy Van <fanwenyi0529@gmail.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      f2b93280
    • Wincy Van's avatar
      KVM: nVMX: Prepare for using hardware MSR bitmap · 3af18d9c
      Wincy Van authored
      Currently, if L1 enables MSR_BITMAP, we will emulate this feature, all
      of L2's msr access is intercepted by L0.  Features like "virtualize
      x2apic mode" require that the MSR bitmap is enabled, or the hardware
      will exit and for example not virtualize the x2apic MSRs.  In order to
      let L1 use these features, we need to build a merged bitmap that only
      not cause a VMEXIT if 1) L1 requires that 2) the bit is not required by
      the processor for APIC virtualization.
      
      For now the guests are still run with MSR bitmap disabled, but this
      patch already introduces nested_vmx_merge_msr_bitmap for future use.
      Signed-off-by: default avatarWincy Van <fanwenyi0529@gmail.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      3af18d9c
  3. 02 Feb, 2015 2 commits
  4. 30 Jan, 2015 6 commits
  5. 29 Jan, 2015 5 commits
  6. 27 Jan, 2015 2 commits
  7. 26 Jan, 2015 7 commits
  8. 23 Jan, 2015 11 commits