- 06 Aug, 2020 23 commits
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Stylon Wang authored
[Why] Setting abm level does not correctly update CRTC state. As a result no surface update is added to dc stream state and triggers warning. [How] Correctly update CRTC state when setting abm level property. CC: Stable <stable@vger.kernel.org> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Bhawanpreet Lakha authored
Use DCN21 functions instead of DCE110 Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Bhawanpreet Lakha authored
[Why] Currently navy_flounder is using sienna_cichlid_dmcub.bin. [How] Create a seperate define so navy_flounder will use its own firmware. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Martin Tsai authored
[Why] Some monitors could suffer symbol unlock but cannot send HPD IRQ to notic source device to handle link loss. This makes monitor stuck in abnormal status and causes black screen. [How] According to the suggestion from scalar vendor, to check lane status again after link training done. That can improve the comaptibility from current production monitors. Signed-off-by: Martin Tsai <martin.tsai@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alvin Lee authored
[Why] In dcn3_update_clocks there are situations where dppclk is not lowered (i.e. stays the same), but DTO still needs to be increased before we program pipe frontend (i.e. in prepare_bandwidth). If we don't program the new DTO value before we program the pipe, we will underflow as soon as the pipe lock is released until the next call to dcn3_update_clocks where the DTO is updated. [How] Remove dppclk check before programming new DTO value. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Eryk Brol authored
[why] Fix naming and return bits rather than bytes per pixel for naming consistency. Because registers return Bytes per pixel, but DSC Config structure is expecting bits per pixel as input. So when returning the value convert from bytes into bits. Signed-off-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Eryk Brol authored
[Why] Struct dcn_dsc_state is used for reading current state and parameters of DSC on a pipe, the target rate parameter uses bytes per pixel even though its reading BITS_PER_PIXEL register. [How] Changing it to Bits Per Pixel for consistency. Signed-off-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Dmytro Laktyushkin authored
[Why] This change replaces older looping code in favor of these functions. [How] There are built in functions for extracting global sync params during mode validation now. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Kevin Wang authored
1. allow asic to handle sensor type by itself. 2. if not, use smu common sensor to handle it. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Dan Carpenter authored
These tables have _COUNT number of elements so the comparisons should be >= instead of > to prevent reading one element beyond the end of the array. Fixes: 8264ee69 ("drm/amd/powerplay: drop unused code") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Likun Gao authored
Update sienna_cichlid driver if header and related files. Support new smu metrics for pre & postDS frequency. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Changfeng authored
Take back patch:drop unnecessary message support check Because the gpu reset fail problem on renoir can be fixed by: drm/amd/powerplay: skip invalid msg when smu set mp1 state It needs to remove SWSMU_CODE_LAYER_L1 in smu_cmn.h to guard a clear code layer. Signed-off-by: changfeng <Changfeng.Zhu@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Boyuan Zhang authored
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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James Zhu authored
jpeg ip block is already selected based on ASIC type during set_ip_blocks. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Likun Gao authored
Update golden setting for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Likun Gao authored
Set valid_in_vf to false for the message not support in vf mode on sienna cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Likun Gao authored
Mapping Mode1Reset message for sienna_cichlid. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Likun Gao authored
Some asic may not support for some message of set mp1 state. If the return value of smu_send_smc_msg is -EINVAL, that means it failed to send msg to smc as it can not map an valid message for the ASIC. And with that case, smu_set_mp1_state should be skipped as those ASIC was in fact do not support for that. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Kenneth Feng authored
It's not necessary to retrieve the power features status when the asic is booted up the first time. This patch can have the features enablement status still checked in suspend/resume case and removed from the first boot up sequence. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Changfeng authored
The below 3 messages are not supported on Renoir SMU_MSG_PrepareMp1ForShutdown SMU_MSG_PrepareMp1ForUnload SMU_MSG_PrepareMp1ForReset It needs to revert patch: drm/amd/powerplay: drop unnecessary message support check to avoid set mp1 state fail during gpu reset on renoir. Signed-off-by: changfeng <Changfeng.Zhu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Guchun Chen authored
This will tell users if the faulty page has been written to external eeprom device in dmesg log. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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John Clements authored
Added dedicated 64bit reg read/write support Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Colin Ian King authored
There is a spelling mistake in a DRM_ERROR error message. Fix it. This got lost in a merge, restore the fix. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 4afaa61d)
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- 04 Aug, 2020 1 commit
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https://gitlab.freedesktop.org/drm/msmDave Airlie authored
Take 2 of msm-next pull, this version drops the OPP patch due to [1], so I'll send the gpu opp/bw scaling patch after the OPP patch lands. Since I had to force-push I took the opportunity to rebase on drm-next, and since you already merged in 5.8-rc6 a few fixes from the last cycle dropped out. This time around: * A bunch more a650/a640 (sm8150/sm8250) display and GPU enablement and fixes * Enable dpu dither block for 6bpc panels * dpu suspend fixes * dpu fix for cursor on 2nd display * dsi/mdp5 enablement for sdm630/sdm636/sdm660 I also regenerated the register headers, which accounts for a good bit of the size this time, because we hadn't re-synced the register headers since the early days of a6xx bringup. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/ <CAF6AEGs_eswoX-E0Ddg5DoEQy35x3GG+6SDXUAjPMrtAWFkqng@mail.gmail.com
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- 31 Jul, 2020 16 commits
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Bernard authored
Use kthread_create_worker to simplify the code and optimise the manager struct: msm_drm_thread. With this change, we could remove struct element (struct task_struct *thread & struct kthread_worker worker), instead, use one point (struct kthread_worker *worker). Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Konrad Dybcio authored
This commit adds support for the MDP5 IP on Snapdragon 636/660. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Konrad Dybcio authored
This also applies to sdm630/636 and their SDA counterparts. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Konrad Dybcio authored
This commit adds support for the MDP5 IP on Snapdragon 630. The configuration is different from SDM660's, as the latter one has two DSI outputs. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Konrad Dybcio authored
These SoCs make use of the 14nm phy, but at different addresses than other 14nm units. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
Initialize hardware clock-gating registers on A640 and A650 GPUs. At least for A650, this solves some performance issues. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
This will allow supporting different hwcg tables for a6xx. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
This brings up basic video mode functionality for SM8250 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
This brings up basic video mode functionality for SM8150 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek <jonathan@marek.ca> [fixup max_linewidth warning] Signed-off-by: Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
Calculate the correct timings for displayport, from downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
This fixes flushing of INTF_2 and INTF_3 on SM8150 and SM8250 hardware. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
The INTF_INPUT_CTRL feature is not available on sdm845, so don't set it. This also adds separate feature bits for INTF (based on downstream) instead of using CTL feature bit for it, and removes the unnecessary NULL check in the added bind_pingpong_blk function. Fixes: 73bfb790 ("msm:disp:dpu1: setup display datapath for SC7180 target") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
This isn't something that ever changes between planes, so move it to dpu_caps struct. Making this change will allow more re-use in the "SSPP sub blocks config" part of the catalog, in particular when adding support for SM8150 and SM8250 which have different max_linewidth. This also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation is not supported on the newest DPU versions. (note that decimation is not implemented, so this changes nothing) Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
Update the UBWC registers to the right values for sm8150 and sm8250. This removes broken dpu_hw_reset_ubwc, which doesn't work because the "force blk offset to zero to access beginning of register region" hack is copied from downstream, where mapped region starts 0x1000 below what is used in the upstream driver. Also simplifies the overly complicated change that was introduced in e4f9bbe9 to work around dpu_hw_reset_ubwc being broken. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
All DPU versions starting from 4.0 use the sdm845 version, so check for that instead of checking each version individually. This chooses the right function for sm8150 and sm8250. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
This is required for A640 and A650 to be able to share UBWC-compressed images with other HW such as display, which expect this configuration. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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