- 26 Feb, 2011 1 commit
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Tomoya MORINAGA authored
fix the following kernel error ------------[ cut here ]------------ WARNING: at kernel/softirq.c:159 _local_bh_enable_ip.clone.5+0x35/0x71() Hardware name: To be filled by O.E.M. Modules linked in: pch_uart pch_dma fuse mga drm cpufreq_ondemand acpi_cpufreq mperf ip6t_REJECT nf_conntrack_ipv6 nf_defrag_ipv6 ip6table_filter ip6_tables ipv6 uinput snd_hda_codec_realtek snd_hda_intel snd_hda_codec matroxfb_base snd_hwdep 8250_pnp snd_seq snd_seq_device matroxfb_DAC1064 snd_pcm joydev 8250 matroxfb_accel snd_timer matroxfb_Ti3026 ppdev pegasus parport_pc snd parport matroxfb_g450 g450_pll serial_core video output matroxfb_misc soundcore snd_page_alloc serio_raw pcspkr ext4 jbd2 crc16 sdhci_pci sdhci mmc_core floppy [last unloaded: scsi_wait_scan] Pid: 0, comm: swapper Not tainted 2.6.37.upstream_check+ #8 Call Trace: [<c0433add>] warn_slowpath_common+0x65/0x7a [<c043825b>] ? _local_bh_enable_ip.clone.5+0x35/0x71 [<c0433b01>] warn_slowpath_null+0xf/0x13 [<c043825b>] _local_bh_enable_ip.clone.5+0x35/0x71 [<c043829f>] local_bh_enable_ip+0x8/0xa [<c06ec471>] _raw_spin_unlock_bh+0x10/0x12 [<f82b57dd>] pd_prep_slave_sg+0xba/0x200 [pch_dma] [<f82f7b7a>] pch_uart_interrupt+0x44d/0x6aa [pch_uart] [<c046fa97>] handle_IRQ_event+0x1d/0x9e [<c047146f>] handle_fasteoi_irq+0x90/0xc7 [<c04713df>] ? handle_fasteoi_irq+0x0/0xc7 <IRQ> [<c04045af>] ? do_IRQ+0x3e/0x89 [<c04035a9>] ? common_interrupt+0x29/0x30 [<c04400d8>] ? sys_getpriority+0x12d/0x1a2 [<c058bb2b>] ? arch_local_irq_enable+0x5/0xb [<c058c740>] ? acpi_idle_enter_bm+0x22a/0x261 [<c0648b11>] ? cpuidle_idle_call+0x70/0xa1 [<c0401f44>] ? cpu_idle+0x49/0x6a [<c06d9fc4>] ? rest_init+0x58/0x5a [<c089e762>] ? start_kernel+0x2d0/0x2d5 [<c089e0ce>] ? i386_start_kernel+0xce/0xd5 Signed-off-by:
Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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- 14 Feb, 2011 4 commits
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Dan Williams authored
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Dan Williams authored
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Dan Williams authored
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Anatolij Gustschin authored
Currently when two or more buffers are queued by the camera driver and so the double buffering is enabled in the idmac, we lose one frame comming from CSI since the reporting of arrival of the first frame is deferred by the DMAIC_7_EOF interrupt handler and reporting of the arrival of the last frame is not done at all. So when requesting N frames from the image sensor we actually receive N - 1 frames in user space. The reason for this behaviour is that the DMAIC_7_EOF interrupt handler misleadingly assumes that the CUR_BUF flag is pointing to the buffer used by the IDMAC. Actually it is not the case since the CUR_BUF flag will be flipped by the FSU when the FSU is sending the <TASK>_NEW_FRM_RDY signal when new frame data is delivered by the CSI. When sending this singal, FSU updates the DMA_CUR_BUF and the DMA_BUFx_RDY flags: the DMA_CUR_BUF is flipped, the DMA_BUFx_RDY is cleared, indicating that the frame data is beeing written by the IDMAC to the pointed buffer. DMA_BUFx_RDY is supposed to be set to the ready state again by the MCU, when it has handled the received data. DMAIC_7_CUR_BUF flag won't be flipped here by the IPU, so waiting for this event in the EOF interrupt handler is wrong. Actually there is no spurious interrupt as described in the comments, this is the valid DMAIC_7_EOF interrupt indicating reception of the frame from CSI. The patch removes code that waits for flipping of the DMAIC_7_CUR_BUF flag in the DMAIC_7_EOF interrupt handler. As the comment in the current code denotes, this waiting doesn't help anyway. As a result of this removal the reporting of the first arrived frame is not deferred to the time of arrival of the next frame and the drivers software flag 'ichan->active_buffer' is in sync with DMAIC_7_CUR_BUF flag, so the reception of all requested frames works. This has been verified on the hardware which is triggering the image sensor by the programmable state machine, allowing to obtain exact number of frames. On this hardware we do not tolerate losing frames. This patch also removes resetting the DMA_BUFx_RDY flags of all channels in ipu_disable_channel() since transfers on other DMA channels might be triggered by other running tasks and the buffers should always be ready for data sending or reception. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Reviewed-by:
Guennadi Liakhovetski <g.liakhovetski@gmx.de> Tested-by:
Dan Williams <dan.j.williams@intel.com>
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- 31 Jan, 2011 35 commits
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Sascha Hauer authored
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Sascha Hauer authored
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Shawn Guo authored
As per the reference manual, bit "L" should be set while bit "C" should be cleared for the last buffer descriptor in the non-cyclic chain, so that sdma can stop trying to find the next BD and end the transfer. In case of sdma_prep_slave_sg(), BD_LAST needs to be set and BD_CONT be cleared for the last BD. Signed-off-by:
Shawn Guo <shawn.guo@freescale.com> Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de>
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Shawn Guo authored
sdma_handle_channel_loop() is the handler of cyclic tx. One period success does not really mean the success of the tx. Instead of DMA_SUCCESS, DMA_IN_PROGRESS should be the one to tell. Signed-off-by:
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Shawn Guo authored
The sdmac->status was designed to reflect the status of the tx, so simply return it in sdma_tx_status(). Then dma client can call dma_async_is_tx_complete() to know the status of the tx. Signed-off-by:
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Shawn Guo authored
sdma_prep_dma_cyclic() sets sdmac->status to DMA_ERROR in err_out, and sdma_prep_slave_sg() needs to do the same. Otherwise, sdmac->status stays at DMA_IN_PROGRESS, which will make the function return immediately next time it gets called. Signed-off-by:
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Shawn Guo authored
This is a leftover from the time that the driver did not have sdma_prep_dma_cyclic callback and implemented sound dma as a looped sg chain. And it can be removed now. Signed-off-by:
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Sascha Hauer authored
The capabilities are device specific fields, not channel specific fields. Signed-off-by: -
Sascha Hauer authored
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Sascha Hauer authored
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Sascha Hauer authored
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Sascha Hauer authored
We need channel 0 of the sdma engine for internal purposes. We accomplished this by calling dma_request_channel() in the probe function. This does not work when multiple dma engines are present which is the case when IPU support for i.MX31/35 is compiled in. So instead of registering channel 0 and reserving it afterwards simply do not register it in the first place. With this the dmaengine channel counting does not match sdma channel counting anymore, so we have to use sdma channel counting in the driver. Signed-off-by: -
Sascha Hauer authored
The capabilities are device specific fields, not channel specific fields. Signed-off-by: -
Sascha Hauer authored
This is bogus as the dmaengine core will overwrite this field. Signed-off-by: -
Sascha Hauer authored
This patch lets sdma_prep_slave_sg fail if the entries of an sg list do not start on multiples of the word size or if the lengths are not multiple of the word size. Also, catch the previously unhandled DMA_SLAVE_BUSWIDTH_8_BYTES and DMA_SLAVE_BUSWIDTH_UNDEFINED cases. Signed-off-by: -
Sascha Hauer authored
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Rabin Vincent authored
Support cyclic transfers, which are useful for ALSA drivers. Acked-by:
Per Forlin <per.forlin@stericsson.com> Acked-by:
Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by:
Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by:
Linus Walleij <linus.walleij@stericsson.com> Signed-off-by:
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Rabin Vincent authored
The current implementation of DMA_TERMINATE_ALL leaves ongoing transfers running. Fix it. Acked-by:
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Rabin Vincent authored
The DMA_SG cap is enabled on the wrong channel, and the pointers are repeatedly set incorrectly. Fix it and combine the ops settings to a common function. Acked-by:
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Rabin Vincent authored
Acked-by:
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Rabin Vincent authored
Acked-by:
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Rabin Vincent authored
Acked-by:
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Rabin Vincent authored
Acked-by:
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Rabin Vincent authored
Acked-by:
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Rabin Vincent authored
Acked-by:
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Rabin Vincent authored
Acked-by:
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Rabin Vincent authored
Acked-by:
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Rabin Vincent authored
These register writes are better placed in the main source file rather than ll.c. Acked-by:
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Rabin Vincent authored
Acked-by:
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Rabin Vincent authored
The dmaengine framework has the API for this now. Acked-by:
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Rabin Vincent authored
Acked-by:
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Rabin Vincent authored
Acked-by:
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Rabin Vincent authored
Acked-by:
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Rabin Vincent authored
The desc init code can be shared between the mem and slave prep routines. Acked-by:
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Rabin Vincent authored
To simplify the code. Acked-by:
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