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  1. 22 Jul, 2022 1 commit
    • Linus Walleij's avatar
      ARM: pxa2xx: Fix GPIO descriptor tables · c5cdb928
      Linus Walleij authored 
      Laurence reports:

"Kernel >5.18 on Zaurus has a bug where the power management code can't
talk to devices, emitting the following errors:

sharpsl-pm sharpsl-pm: Error: AC check failed: voltage -22.
sharpsl-pm sharpsl-pm: Charging Error!
sharpsl-pm sharpsl-pm: Warning: Cannot read main battery!

Looking at the recent changes, I found that commit 31455bbd ("spi:
pxa2xx_spi: Convert to use GPIO descriptors") replaced the deprecated
SPI chip select platform device code with a gpiod lookup table. However,
this didn't seem to work until I changed the `dev_id` member from the
device name to the bus id. I'm not entirely sure why this is necessary,
but I suspect it is related to the fact that in sysfs SPI devices are
attached under /sys/devices/.../dev_name/spi_master/spiB/spiB.C, rather
than directly to the device."

After reviewing the change I conclude that the same fix is needed
for all affected boards.

Fixes: 31455bbd ("spi: pxa2xx_spi: Convert to use GPIO descriptors")
Reported-by: default avatarLaurence de Bruxelles <lfdebrux@gmail.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220722114611.1517414-1-linus.walleij@linaro.org'
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
      c5cdb928
  3. 21 Jul, 2022 1 commit
  5. 20 Jul, 2022 1 commit
  7. 18 Jul, 2022 1 commit
    • Michael Walle's avatar
      ARM: dts: lan966x: fix sys_clk frequency · ef0324b6
      Michael Walle authored 
      The sys_clk frequency is 165.625MHz. The register reference of the
Generic Clock controller lists the CPU clock as 600MHz, the DDR clock as
300MHz and the SYS clock as 162.5MHz. This is wrong. It was first
noticed during the fan driver development and it was measured and
verified via the CLK_MON output of the SoC which can be configured to
output sys_clk/64.

The core PLL settings (which drives the SYS clock) seems to be as
follows:
  DIVF = 52
  DIVQ = 3
  DIVR = 1

With a refernce clock of 25MHz, this means we have a post divider clock
  Fpfd = Fref / (DIVR + 1) = 25MHz / (1 + 1) = 12.5MHz

The resulting VCO frequency is then
  Fvco = Fpfd * (DIVF + 1) * 2 = 12.5MHz * (52 + 1) * 2 = 1325MHz

And the output frequency is
  Fout = Fvco / 2^DIVQ = 1325MHz / 2^3 = 165.625Mhz

This all adds up to the constrains of the PLL:
    10MHz <= Fpfd <= 200MHz
    20MHz <= Fout <= 1000MHz
  1000MHz <= Fvco <= 2000MHz

Fixes: 290deaa1 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291")
Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Reviewed-by: default avatarKavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220326194028.2945985-1-michael@walle.cc
      ef0324b6
  9. 17 Jul, 2022 15 commits
  11. 16 Jul, 2022 12 commits
  13. 15 Jul, 2022 9 commits
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