- 22 Oct, 2021 7 commits
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Alex Deucher authored
Roughly the same code was present in all VCN versions. Consolidate it into a single function. v2: use AMDGPU_UCODE_ID_VCN + i, check if num_inst >= 2 Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com>
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Alex Deucher authored
Only enable firmware for the instance that is enabled. v2: use AMDGPU_UCODE_ID_VCN + i Fixes: 1b592d00 ("drm/amdgpu/vcn: remove manual instance setting") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1743Reviewed-by:
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Philip Yang authored
Not all migrate.cpages returned from migrate_vma_setup can be migrated, for example non anonymous page, or out of device memory. So after migrate_vma_pages returns, add debug message to count pages are successfully migrated which has MIGRATE_PFN_VALID and MIGRATE_PFN_MIGRATE flag set. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Philip Yang authored
cpages is only updated by migrate_vma_setup. So capture its value at that point to clarify the significance of the number. The next patch will add counting of actually migrated pages after migrate_vma_pages for debug purposes. Signed-off-by:
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Jingwen Chen authored
Add dummy_page_addr to sriov msg for host driver to set GCVM_L2_PROTECTION_DEFAULT_ADDR* registers correctly. v2: should update vf2pf msg instead Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by:
Horace Chen <horace.chen@amd.com> Signed-off-by:
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Huang Rui authored
PSP firmware will be responsible for applying the GRBM CAM remapping in the production. And the GRBM_CAM_INDEX / GRBM_CAM_DATA registers will be protected by PSP under security policy. So remove it according to the new security policy. Signed-off-by:
Huang Rui <ray.huang@amd.com> Acked-by:
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Vignesh Chander authored
Enable GPU metrics feature in one VF mode. These are only possible in one VF mode because the VF is dedicated in that case. Signed-off-by:
Vignesh Chander <Vignesh.Chander@amd.com> Reviewed-by:
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- 20 Oct, 2021 10 commits
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Kent Russell authored
Change the error message when the bad_page_threshold is reached, explicitly stating that the GPU will not be initialized. Cc: Luben Tuikov <luben.tuikov@amd.com> Cc: Mukul Joshi <Mukul.Joshi@amd.com> Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Alex Deucher authored
No longer used since IP enumeration is driven by the IP discovery table now. Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Alex Deucher authored
No longer used since IP enumeration is now driven by amdgpu IP discovery code. Acked-by:
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Alex Deucher authored
No longer used since IP enumeration is now driven by amdgpu IP discovery code. Acked-by:
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Alex Deucher authored
raven_device_info is not used when KFD_SUPPORT_IOMMU_V2 is not set. Reviewed-by:
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Alex Deucher authored
hawaii_device_info is not used when CONFIG_DRM_AMDGPU_CIK is not set. Reviewed-by:
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Alex Deucher authored
Check was incorrectly converted to IP version checking. Fixes: 4b0ad842 ("drm/amdgpu/gfx10: convert to IP version checking") Reviewed-by:
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Alex Deucher authored
When selecting between levels in the force performance levels interface sclk (gfxclk) was not set correctly for all levels. Select the proper sclk settings for all levels. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1726Reviewed-by:
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Qing Wang authored
show() must not use snprintf() when formatting the value to be returned to user space. Fix the following coccicheck warning: drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:427: WARNING: use scnprintf or sprintf. Signed-off-by:
Qing Wang <wangqing@vivo.com> Signed-off-by:
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Aaron Liu authored
B0 internal rev_id is 0x01, B1 internal rev_id is 0x02. The external rev_id for B0 and B1 is 0x20. The original expression is not suitable for B1. v2: squash in fix for display code (Alex) Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
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- 19 Oct, 2021 23 commits
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Guchun Chen authored
Otherwise, hw_id_name string is NULL for SDMA 2 and 3 when dumping ip version from VBIOS. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
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Tao Zhou authored
Output a warning message if RAS TA returns UNSUPPORTED_ERROR_INJ status. v2: implement it in psp_ras_ta_check_status function. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Tao Zhou authored
Create new function to check status returned by RAS TA. Signed-off-by:
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Agustin Gutierrez authored
This reverts commit 1445d967. This patch introduced a couple of dmesg warnings, this is not a valid approach anymore. For this reason, we are reverting this patch, and we need to revert the workaround patch. v2: squash in unused variable removal (Alex) Cc: Hanghong Ma <hanghong.ma@amd.com> Cc: Mark Broadworth <mark.broadworth@amd.com> Signed-off-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Signed-off-by:
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Agustin Gutierrez authored
This reverts commit 4874ecf5. Signed-off-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Nevenko Stupar authored
[Why] V3_4 is latest in use. [How] Add bios parser support for firmware_info_v3_4 along with some relevant fields it is also retrieving from dce_info and smu_info. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Tested-by:
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Aric Cyr authored
This DC patchset brings improvements in multiple areas. In summary, we highlight: * Fix some issues such as DP2 problem, prefetch bandwidth calculation for DCN3.1 and others. * Increased Z9 latency and removed z10 save after dsc disable. * Revert a couple of bad changes. * Added missing PSR state patch. Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Anthony Koo authored
Acked-by:
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Jake Wang authored
[Why & How] Disable hdmistream and hdmichar root clocks when not being used. Reviewed-by:
Jake Wang <haonan.wang2@amd.com> Tested-by:
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Jake Wang authored
[Why] bios_golden_init will override dccg_init during init_hw. [How] Move dccg_init to after bios_golden_init. Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Jake Wang authored
[Why & How] Z10 save is done during PSR and bootup. DSC disable does not need to save for Z10. Reviewed-by:
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Jake Wang authored
[Why & How] Disable dpstreamclk, symclk32_se, and symclk32_le when not in use. Reviewed-by:
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Nikola Cornij authored
[why] The original latencies were causing underflow in some modes [how] Replace with the up-to-date watermark values based on new measurments Reviewed-by:
Ahmad Othman <ahmad.othman@amd.com> Acked-by:
Nikola Cornij <nikola.cornij@amd.com> Tested-by:
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Eric Yang authored
[Why] Z9 latency is higher than when we originally tuned the watermark parameters, causing underflow. Increasing the value until the latency issues is resolved. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] Immediate flip can be enabled dynamically and has higher BW requirements when validating which voltage mode to use. If we validate when it's not set then potentially DCFCLK will be too low and we will underflow. [How] DM always requires support so always require it as part of DML input parameters. This can't be enabled unconditionally on older ASIC because it blocks some expected modes so only target DCN3.1 for now. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Jake Wang authored
[Why & How] Disable root clock for dsc when not being used. Reviewed-by:
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Mikita Lipski authored
[why] PSR_STATE2b was introduced on DMCUB side, but not on the driver side, which caused convert_psr_state helper function to return PSR_STATE_INVALID. That caused visual lagging during state transition. [how] Add PSR_STATE2b to dc_psr_state and convert_psr_state Reviewed-by:
Wyatt Wood <Wyatt.Wood@amd.com> Acked-by:
Mikita Lipski <mikita.lipski@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] Prefetch BW calculated is lower than the DML reference because of a porting error that's excluding cursor and row bandwidth from the pixel data bandwidth. [How] Change the dml_max4 to dml_max3 and include cursor and row bandwidth in the same calculation as the rest of the pixel data during vactive. Reviewed-by:
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Hansen authored
Remap phyd32clk to PHYF and PHYG for B0, PHYC and PHYD are unused Reviewed-by:
Hansen <Hansen.Dsouza@amd.com> Tested-by:
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Nikola Cornij authored
[why] The requirement is that image width up to 4096 shall be supported Reviewed-by:
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Lai, Derek authored
[Why] Error message on Linux when booting. [How] Removed power down on boot from DCN31 HW init to match DCN10 HW init. Reviewed-by:
Derek Lai <derek.lai@amd.com> Tested-by:
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Aric Cyr authored
[Why] Calculation of scaling ratio can result in a crash due to zero'd src or dst plane rects. [How] Validate that src and dst rects are valid before using for scaling calculations. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
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