- 19 Feb, 2018 40 commits
-
-
Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Charlene Liu authored
Signed-off-by:
-
Tony Cheng authored
Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
-
John Barberiz authored
Signed-off-by:
John Barberiz <jbarberi@amd.com> Reviewed-by:
-
Yongqiang Sun authored
System soft hang when hotplug specific 4K DP panel due to link caps read error and incorrect link setting parmas to enable dp. Add status check for DPCD read and add return value for detect dp, in case of false, return from caller, avoid further false operation. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
-
Roman Li authored
Fixing null-deref on Vega10 due to regression after 'fix cursor related Pstate hang' change. Added null checks in setting cursor position. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Reviewed-by:
-
Nikola Cornij authored
Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
-
Eric Yang authored
As a precaution to prevent cases where cursor is enabled on a pipe that is disabled, always turn off cursor when disconnecting plane. Signed-off-by:
-
Eric Bernstein authored
Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
-
Ken Chalmers authored
* Previous code did some calculations with a mix of normal integers and integers aligned as U2.24 fixed-point values. * There were bugs in the conversion of the final result into the S4.19 values required for the registers. Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
-
Eric Yang authored
Signed-off-by:
-
Eric Yang authored
Move cursor programming to inside the OTG_MASTER_UPDATE_LOCK If graphics plane go from 1 pipe to hsplit, the cursor updates after mpc programming and unlock. Which means there is a window of time where cursor is enabled on the wrong pipe if it's on the right side of the screen (i.e. case where cursor need to move from pipe 0 to pipe 3 post split). This will cause pstate hang. Solution is to program the cursor while still locked. Signed-off-by:
-
Mikita Lipski authored
Because AMDGPU_CRTC_IRQ_VLINE1 = 6, it expected 6 more crtcs to be programed with disabled irq state in amdgpu_irq_disable_all. That caused errors and accessed the wrong memory location. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
-
Yongqiang Sun authored
Signed-off-by:
-
Yongqiang Sun authored
When disable plane, check power gate flag in hubp with pipe_ctx, not with res_pool. Signed-off-by:
-
Christian König authored
Otherwise we might overwrite stuff which is still in use. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
-
Tony Cheng authored
Signed-off-by:
-
John Barberiz authored
If non-standard gamma type detected set identity matrix flag so that we can bypass the gamma mode. Signed-off-by:
-
Charlene Liu authored
Signed-off-by:
-
Leo (Sunpeng) Li authored
If CONFIG_DEBUG_FS is disabled, then CRC should also be disabled. Therefore, amdgpu_dm_crtc_handle_crc_irq was redefined as a no-op function within amdgpu_dm.h. However, since amdgpu_dm.h is included in multiple files, this caused conflicts when linking during compile. Therefore, Use a macro to define the function as a no-op instead. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
-
Jerry (Fangzhi) Zuo authored
There is no need to call drm_mode_set_crtcinfo() again once crtc timing is decided. Otherwise non-native/unsupported timing might get overwritten. Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
-
Martin Tsai authored
Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
-
Charlene Liu authored
Signed-off-by:
-
Harry Wentland authored
Signed-off-by:
-
Christian König authored
It also needs to be initialized. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
-
Christian König authored
Without it we run into a memory leak. Signed-off-by:
-
Alex Deucher authored
No longer used since we changed the MC programming sequence. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
-
Alex Deucher authored
Using the wrong mask. Reviewed-by:
Hans de Ruiter <hans@keasigmadelta.com> Signed-off-by:
-
Arnd Bergmann authored
Building the amd display driver with link-time optimizations revealed a bug that caused dal_cmd_tbl_helper_dce80_get_table() and dal_cmd_tbl_helper_dce110_get_table() get called with an incompatible return type between the two callers in command_table_helper.c and command_table_helper2.c: drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.h:31: error: type of 'dal_cmd_tbl_helper_dce80_get_table' does not match original declaration [-Werror=lto-type-mismatch] const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void); drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.c:351: note: 'dal_cmd_tbl_helper_dce80_get_table' was previously declared here const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void) drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.h:32: error: type of 'dal_cmd_tbl_helper_dce110_get_table' does not match original declaration [-Werror=lto-type-mismatch] const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void); drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.c:361: note: 'dal_cmd_tbl_helper_dce110_get_table' was previously declared here const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void) The two versions of the structure are obviously derived from the same one, but have diverged over time, before they got added to the kernel. This moves the structure to a new shared header file and uses the superset of the members, to ensure the interfaces are all compatible. Fixes: ae79c310 ("drm/amd/display: Add DCE12 bios parser support") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
-
Christian König authored
Beneficial when a lot of processes are waiting for VMIDs. Signed-off-by:
-
Christian König authored
Now that we have the different cases for grabbing a VMID in separate functions, restructure the top level function to only have one place where VMIDs are assigned to jobs. Signed-off-by:
-
Christian König authored
Let's try this once more. Signed-off-by:
-
Christian König authored
Drop the "_locked" from the name, cleanup and simplify the logic a bit. Add missing comments. Signed-off-by:
-
Christian König authored
We do this later on when we flush the VMID anyway. Signed-off-by:
-
Christian König authored
The variable is protected by the VMID mutex anyway. v2: grab the mutex while resetting the VMID as well Signed-off-by:
-
Christian König authored
No functional change, but makes it easier to maintain the code. Signed-off-by:
-
Christian König authored
Similar to finding an idle one before reuse. This guarantees fairness between processes. Otherwise process with a reserved VMID have an unfair advantage while scheduling jobs. v2: improve commit message Signed-off-by:
-
Bas Nieuwenhuizen authored
If these bos are evicted and are in the validated list things blow up, so do not put them in there. Notably, that tries to add the bo to the LRU twice, which results in a BUG_ON in ttm_bo.c. While for the bo_list an alternative would be to not allow always valid bos in there, that does not work for the user fence. v2: Fixed whitespace issue pointed out by checkpatch.pl Signed-off-by:
Bas Nieuwenhuizen <basni@chromium.org> Reviewed-by:
-
Andrey Grodzovsky authored
This reverts commit 75737cb4. Fixes compute rings test failure on bare metal during full GPU reset. RCA: the ring buffer has to be filled with valid packets (such as NOPs) first before submitting MAP_QUEUEs packet into KIQ. Once a compute engine is mapped, it will immediately execute the ring buffer if the RTPR is not equal to the WTPR from the MQD. It could lead to engine hang if the ring buffer filled with random data. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
-
Christian König authored
Keep that at a common place instead of spread over all engines. Signed-off-by:
-
