- 16 Jun, 2009 15 commits
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Kenji Kaneshige authored
Create symbolic link to hotplug driver module in the PCI slot directory (/sys/bus/pci/slots/<SLOT#>). In the past, we need to load hotplug drivers one by one to identify the hotplug driver that handles the slot, and it was very inconvenient especially for trouble shooting. With this change, we can easily identify the hotplug driver. Signed-off-by:
Taku Izumi <izumi.taku@jp.fujitsu.com> Signed-off-by:
Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Reviewed-by:
Alex Chiang <achiang@hp.com> Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org>
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Kenji Kaneshige authored
Current has_foo() functions in pci_hotplug_core.c returns 0 if the "foo" property is true. It would cause misunderstanding. In addition, the error code of those functions is never checked, so this patch changes those functions' error code to 'bool' and return true if the property "foo" is true. Signed-off-by:
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Kenji Kaneshige authored
The EMI support in pciehp is obviously broken. It is implemented using struct hotplug_slot_attribute, but sysfs_ops for pci_slot_ktype is NOT for struct hotplug_slot_attribute, but for struct pci_slot_attribute. This bug had been there for a long time, maybe it was introduced when PCI slot framework was introduced. The reason why this bug didn't cause any problem is maybe the EMI support is not tested at all because of lack of test environment. As described above, the EMI support in pciehp seems not to be tested at all. So this patch removes EMI support from pciehp, instead of fixing the bug. Signed-off-by:
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Andreas Herrmann authored
Describe check_enable_amd_mmconf. Signed-off-by:
Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by:
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Huang Ying authored
This patch adds a minimal HOWTO for PCIE AER software error injection in Documentation/PCI/pcieaer-howto.txt. Signed-off-by:
Huang Ying <ying.huang@intel.com> Signed-off-by:
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Huang Ying authored
This is used by PCIE AER error injection to fake an PCI AER interrupt. Signed-off-by:
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Huang Ying authored
pci_bus_set_ops changes pci_ops associated with a pci_bus. This can be used by debug tools such as PCIE AER error injection to fake some PCI configuration registers. Acked-by:
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Kenji Kaneshige authored
Use pci_is_root_bus() in pci_common_swizzle() for checking if the pci bus is root, for code consistency. Reviewed-by:
Grant Grundler <grundler@parisc-linux.org> Signed-off-by:
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Kenji Kaneshige authored
Use pci_is_root_bus() in pci_get_interrupt_pin() for checking if the pci bus is root, for code consistency. Reviewed-by:
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Kenji Kaneshige authored
Use pci_is_root_bus() in pci_read_bridge_bases() to check if the pci bus is root, for code consistency. Reviewed-by:
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Kenji Kaneshige authored
Use pci_is_root_bus() in pci_find_upstream_pcie_bridge() to check if the pci bus is root, for code consistency. Reviewed-by:
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Kenji Kaneshige authored
Use pci_is_root_bus() in acpi_find_root_bridge_handle() to check if the pci bus is root, for code consistency. Reviewed-by:
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Kenji Kaneshige authored
Use pci_is_root_bus() in acpi_pci_get_bridge_handle() to check if the pci bus is root, for code consistency. Reviewed-by:
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Michal Miroslaw authored
I found no references to SMBus in ACPI DSDT disassembly on my laptop so this should be safe. Signed-off-by:
Michal Miroslaw <mirq-linux@rere.qmqm.pl> Signed-off-by:
Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Michal Miroslaw authored
Some BIOSes hide 'overflow' device (dev #6) for i82875P/PE chipsets. The same happens for i82865P/PE. Add a quirk to enable this device. This allows i82875 EDAC driver to bind to chipset's dev #6 and not dev #0 as the latter is used by AGP driver. On my laptop (i82865P based) ACPI code is disabling this device again in \_SB.PCI0._CRS method (called at least at PNP init time). This can be easily worked around by patching DSDT. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by:
Doug Thompson <norsk5@yahoo.com> Signed-off-by:
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- 11 Jun, 2009 25 commits
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Mats Erik Andersson authored
Addition of one unknown subsystem identifier to the quirks handler for chipset i82855GM_HB on notebook Asus A6L. This exposes the otherwise hidden SMBus controller within the south bridge ICH4-M. Signed-off-by:
Mats Erik Andersson <mats.andersson@gisladisker.se> Signed-off-by:
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Andrew Patterson authored
Adds support for PCI Express transaction layer end-to-end CRC checking (ECRC). This patch will enable/disable ECRC checking by setting/clearing the ECRC Check Enable and/or ECRC Generation Enable bits for devices that support ECRC. The ECRC setting is controlled by the "pci=ecrc=<policy>" command-line option. If this option is not set or is set to 'bios", the enable and generation bits are left in whatever state that firmware/BIOS set them to. The "off" setting turns them off, and the "on" option turns them on (if the device supports it). Turning ECRC on or off can be a data integrity versus performance tradeoff. In theory, turning it on will catch more data errors, turning it off means possibly better performance since CRC does not need to be calculated by the PCIe hardware and packet sizes are reduced. Signed-off-by:
Andrew Patterson <andrew.patterson@hp.com> Signed-off-by:
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Rafael J. Wysocki authored
According to the PCI PM specification (PCI Bus Power Management Interface Specification, Rev. 1.2, Section 5.4.1) we are supposed to reinitialize devices that have PCI_PM_CTRL_NO_SOFT_RESET clear during all transitions from PCI_D3hot to PCI_D0, but we only do it if the device's current_state field is equal to PCI_UNKNOWN. This may lead to problems if a device with PCI_PM_CTRL_NO_SOFT_RESET unset is put into PCI_D3hot at run time by its driver and pci_set_power_state() is used to put it back into PCI_D0, because in that case the device will remain uninitialized after pci_set_power_state() has returned. Prevent that from happening by modifying pci_raw_set_power_state() to reinitialize devices with PCI_PM_CTRL_NO_SOFT_RESET unset during all transitions from D3 to D0. Cc: stable@kernel.org Signed-off-by:
Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by:
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Yu Zhao authored
PCIe root complex integrated endpoint does not implement ARI, so this kind of endpoint uses 3-bit function number. The function dependency link of the integrated endpoint should be calculated using the device number plus the value from function dependency link register. Normal endpoint always implements ARI and the function dependency link register contains 8-bit function number (i.e. `devfn' from software's perspective). Signed-off-by:
Yu Zhao <yu.zhao@intel.com> Signed-off-by:
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Alex Chiang authored
We always call pci_stop_bus_device before calling pci_destroy_dev. Since pci_stop_bus_device calls pci_stop_dev, there is no need for pci_destroy_dev to repeat the call. Signed-off-by:
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Michael S. Tsirkin authored
pci_enable_msix currently returns -EINVAL if you ask for more vectors than supported by the device, which would typically cause fallback to regular interrupts. It's better to return the table size, making the driver retry MSI-X with less vectors. Reviewed-by:
Matthew Wilcox <willy@linux.intel.com> Signed-off-by:
Michael S. Tsirkin <mst@redhat.com> Signed-off-by:
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Shaohua Li authored
VIA has a strange chipset, it has root port under a bridge. Disable ASPM for such strange chipset. Cc: stable@kernel.org Tested-by:
Wolfgang Denk <wd@denx.de> Signed-off-by:
Shaohua Li <shaohua.li@intel.com> Signed-off-by:
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Jesse Barnes authored
At this point, it seems to solve more problems than it causes, so let's try using it by default. It's an easy revert if it ends up causing trouble. Reviewed-by:
Yinghai Lu <yhlu.kernel@gmail.com> Acked-by:
Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by:
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Alex Chiang authored
The last in-tree caller of pci_find_slot has been converted, so let's get rid of this deprecated interface. Signed-off-by:
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Alex Chiang authored
Convert uses of pci_find_slot to modern API. In the conversion sites, we end up calling pci_dev_put() right away. This may seem like it misses the entire point of doing something like pci_get_bus_and_slot(), since we drop the reference so soon, but it turns out we don't actually do much with the returned pci_dev. I plan on untangling cpqphp further, but clearly cpqphp never worried too much about a properly refcounted pci_dev anyway. For now, this conversion seems reasonable, as it gets rid of the last in-tree caller of pci_find_slot. Signed-off-by:
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Alex Chiang authored
Eliminate this warning: warning: return discards qualifiers from pointer target type Signed-off-by:
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Alex Chiang authored
I have no clue what the original intent here was, but the code as written is useless. The old dbg() statement above the old callsite might lead one to think that at one point, there was supposed to be some recursion, but any sense of sanity here has been lost to the ravages of time. Signed-off-by:
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Alex Chiang authored
Instead of making multiple calls to pcibios_get_irq_routing_table, let's just do it once and save the answer. The reason we were making multiple calls is because we liked to calculate its length and perform some loop over it. Instead of open-coding the length calculation every time, provide it in an inline helper function. Finally, since pci_print_IRQ_route() is used only for debug, let's only do it when cpqhp_debug is set. Signed-off-by:
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Alex Chiang authored
Handle an empty slot at the top of the loop, and continue early. This allows us to un-indent the rest of the function by one level. Signed-off-by:
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Alex Chiang authored
Clean up style, whitespace in cpqphp_pci.c Signed-off-by:
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Alex Chiang authored
Check for an empty slot, and return early if so. This allows us to un-indent the rest of the function by one level. Signed-off-by:
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Alex Chiang authored
Style and whitespace cleanups, no functional change. Signed-off-by:
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Alex Chiang authored
Apply DeMorgan's theorem: if ((pdev->revision > 2) || (vendor_id == PCI_VENDOR_ID_INTEL)) turns into if ((pdev->revision <= 2) && (vendor_id != PCI_VENDOR_ID_INTEL)) Now we can bail out early from the function if the controller is not supported. This allows us to un-indent the remainder of the function quite a bit and make it much more readable. Fix up some extra braces, and un-indent the 'case' labels in the switch statement as per CodingStyle. No functional change. Signed-off-by:
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Alex Chiang authored
Clean up style and eliminate superfluous braces and parens. No functional change. Signed-off-by:
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Alex Chiang authored
Impact: refactor Refactor code to follow convention more closely and eliminate the need for some useless prototypes. No functional change. Signed-off-by:
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Alex Chiang authored
Clean up cpqphp.h to follow 80 column convention. Signed-off-by:
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Alex Chiang authored
Fix up comments from C++ to C-style, wrapping if necessary, etc. Signed-off-by:
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Alex Chiang authored
Clean up all stray whitespace issues, such as trailing whitespace, spaces before tabs, etc. and whatever else vim's c_space_errors highlights in red. Signed-off-by:
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Yinghai Lu authored
We could run out of space under under 4g, but devices under transparent bridges can use 64bit resources, so keep trying on the parent bus until we hit a non-transparent bridge. Impact: better support for assigning unassigned resources Reviewed-by:
Ivan Kokshaysky <ink@jurassic.park.msu.ru> Signed-off-by:
Yinghai Lu <yinghai@kernel.org> Signed-off-by:
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Yinghai Lu authored
We should not assign 64bit ranges to PCI devices that only take 32bit prefetchable addresses. Try to set IORESOURCE_MEM_64 in 64bit resource of pci_device/pci_bridge and make the bus resource only have that bit set when all devices under it support 64bit prefetchable memory. Use that flag to allocate resources from that range. Reported-by:
Yannick <yannick.roehlly@free.fr> Reviewed-by:
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