- 05 Jun, 2014 9 commits
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Akash Goel authored
For disabling L3 clock gating we need to set bit 25 of MMIO register 940c. Earlier this was being done by just writing 1 into bit 25 and resetting all other bits. This patch modifies the routine to read-modify-write of the register, so that the values of other bits are not destroyed. v2: Modifying the comments and the patch commit message (Chris) Signed-off-by:
Akash Goel <akash.goel@intel.com> Signed-off-by:
Sourab Gupta <sourab.gupta@intel.com> Reviewed-by:
Damien Lespiau <damien.lespiau@intel.com> [danvet: Apply checkpatch fixup.] Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Shobhit Kumar authored
This driver makes use of the generic panel information from the VBT. Panel information is classified into two - panel configuration and panel power sequence which is unique to each panel. The generic driver uses the panel configuration and sequence parsed from VBT block #52 and #53 v2: Address review comments by Jani - Move all of the things in driver c file from header - Make all functions static - Make use of video/mipi_display.c instead of redefining - Null checks during sequence execution v3: Address review comments by Damien - Rename the panel driver file as intel_dsi_panel_vbt.c - Fix style changes as suggested - Correct comments for lp->hs and hs->lp count calculations - General updating comments to have more clarity - using max() instead of ternary operator - Fix names (ui_num, ui_den) while using UI in calculations - compute max of lp_to_hs switch and hs_to_lp switch while computing hs_lp_switch_count Signed-off-by:Shobhit Kumar <shobhit.kumar@intel.com> Reviewed-by:
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Daniel Vetter authored
Fallout from an intermediate patch revision that I deemed worth saving. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Daniel Vetter authored
Currently we do a full re-init of all interrupts after a gpu hang. Which is pretty bad since we don't restore the interrupts we've enabled at runtime correctly. Even with that addressed it's rather horribly race. But on g4x and later we only reset the gt and not the entire gpu. Which means we only need to reset the GT interrupt bits. Which has the nice benefit that vblank waits, pipe CRC interrupts and everything else display related just keeps on working. The downside is that gt interrupt handling (i.e. ring->get/put_irq) is still racy. But as long as the gpu hang reliably wakes all waters and we have a short time where the refcount drops to 0 we'll recover. So not that bad really. v2: Ville noticed that GTIMR and PMIMR don't get cleared, only the subordinate per-ring registers. So let's rip out all the interrupt dancing. The FIXME comment is still required though since the ring irq handling happens at the per-ring interrupt mask registers, too. Testcase: igt/kms_flip/vblank-vs-hang Testcase: igt/kms_pipe_crc_basic/hang-* Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Daniel Vetter authored
No point in having this indirection. Reviewed-by:
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Daniel Vetter authored
Ville figured out that it needs a full display reset since apparently a lot more goes down than just the GT. Until that's address it's better to just diable gpu reset. Reviewed-by:
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Daniel Vetter authored
So apparently this is tricky. We need to consider: - We start out with all the hw enabling bits disabled, both the individual fifo underrun interrupts and the shared display error interrupts masked. Otherwise if the bios config is broken we'll blow up with a NULL deref in our interrupt handler since the crtc structures aren't set up yet at driver load time. - On gmch we need to mask fifo underruns on the sw side, so always need to set that in sanitize_crtc for those platforms. - On other platforms we try to set the sw tracking so that it reflects the real state. But since a few platforms have shared bits we must _not_ disable fifo underrun reporting. Otherwise we'll never enable the shared error interrupt. This is the state before out patch, but unfortunately this is not good enough. But after a suspend resume operation this is broken: 1. We don't enable the hw interrupts since the same code runs on resume as on driver load. 2. The fifo underrun state adjustments we do in sanitize_crtc doesn't fire on resume since (except for hilarious firmware) all pipes are off at that point. But they also don't hurt since the subsequent crtc enabling due to force_restore will enable fifo underruns. Which means when we enable fifo underrun reporting we notice that the per-crtc state is already correct and short-circuit everthing out. And the interrupt doesn't get enabled. A similar problem would happen if the bios doesn't light up anything when the driver loads. Which is exactly what happens when we reload the driver since our unload functions disables all outputs. Now we can't just rip out the short-circuit logic and unconditionally update the fifo underrun reporting interrupt masking: We have some checks for shared error interrupts to catch issues that happened when the shared error interrupt was disabled. The right fix is to push down this logic so that we can always update the hardware state, but only check for missed fifo underruns on a real enabled->disabled transition and ignore them when we're already disabled. On platforms with shared error interrupt the pipe CRC interrupts are grouped together with the fifo underrun reporting this fixes pipe CRC support after suspend and driver reloads. Testcase: igt/kms_pipe_crc_basic/suspend-* Reviewed-by:
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Daniel Vetter authored
On platforms with shared interrupt enable bits (which are shared even with the pipe CRC logic) there's some tricky corner cases. Add information to make debugging those easier. Reviewed-by:
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Rob Clark authored
All drm_fb_helper_restore_fbdev_mode() call sites, save one, do the same locking. Simplify this into drm_fb_helper_restore_fbdev_mode_unlocked(). Signed-off-by:
Rob Clark <robdclark@gmail.com> Reviewed-by:
Dave Airlie <airlied@redhat.com>
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- 04 Jun, 2014 23 commits
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Rob Clark authored
For atomic, it will be quite necessary to not need to care so much about locking order. And 'state' gives us a convenient place to stash a ww_ctx for any sort of update that needs to grab multiple crtc locks. Because we will want to eventually make locking even more fine grained (giving locks to planes, connectors, etc), split out drm_modeset_lock and drm_modeset_acquire_ctx to track acquired locks. Atomic will use this to keep track of which locks have been acquired in a transaction. v1: original v2: remove a few things not needed until atomic, for now v3: update for v3 of connection_mutex patch.. v4: squash in docbook v5: doc tweaks/fixes Signed-off-by:
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Dave Airlie authored
This should avoid races between connector probing and HPD irqs in the future, currently mode_config.mutex blocks this possibility. Reviewed-by:
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
Just flushing out my pile of random drm patches for the merge window, nothing big. And it all hung around in drm-intel trees for a while (only just rebased now). * tag 'topic/core-stuff-2014-06-02' of git://anongit.freedesktop.org/drm-intel: imx-drm: imx-tve: remove unused variable drm: Missed clflushopt in drm_clflush_virt_range drm/plane: Fix a couple of checkpatch warnings drm/plane: Fix sparse warnings drm/exynos: Fix double locks at PM resume drm/ast: Fix double lock at PM resume drm/dp-helper: Deprecate old i2c-over-dp_aux heleprs
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Dave Airlie authored
Merge branch 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next Summary: - Resolve probe order and deferred probe issue with component framework support. - Resolve hdmi dt broken issue. . HDMI DT support, which was broken since CCF (common clock framework) support, and considring legacy dt binding. - Consolidate HDMI part. . APB based phy support for Exynos5420 and later, and fixups related to power on/off sequence. - Consolidate IPP part. . Mostly bug fixups and code cleanups. - Trivial fixups and code cleanups. * 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos: (64 commits) drm/exynos: consider deferred probe case drm/exynos: remove unnecessary exynos_hdmi.h file drm/exynos/fimd: allow multiplatform configuration drm/exynos: add hdmiphy power on/off sequence drm/exynos: ipp: remove description of non-existing field drm/exynos: ipp: update comment for struct drm_ipp_buf_info drm/exynos: ipp: rearrange c_node->event_lock using routine drm/exynos: ipp: rearrange c_node->mem_lock using routines drm/exynos: ipp: add ipp_remove_id() drm/exynos: ipp: add cmd_lock for cmd_list drm/exynos: ipp: rename cmd_lock to lock drm/exynos: ipp: remove duplicated setting drm/exynos: ipp: remove usless list_empty() functions drm/exynos: Use PTR_ERR_OR_ZERO in exynos_dp_core.c drm/exynos: remove hardware overlays disable from fimd probe drm/exynos: Fix checkpatch warning in exynos_dp_reg.c drm/exynos: add fimd dependency to fimd related encoders drm/exynos: remove redundant mutex_unlock drm/exynos/fimc: simplify and rename fimc_dst_get_buf_seq drm/exynos/fimc: replace mutex by spinlock ...
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git://people.freedesktop.org/~robclark/linuxDave Airlie authored
Pretty small pull this time around for msm. Adds some useful debugfs I'd been carrying around on a branch for a while, plus few fixes. And Kconfig update for the great ARCH_MSM -> ARCH_QCOM split. * 'msm-next' of git://people.freedesktop.org/~robclark/linux: drm/msm: use correct gfp flag for vram allocation drm/msm/mdp5: fix error return value drm/msm: remove redundant private plane cleanup drm/msm: add perf logging debugfs drm/msm: add rd logging debugfs drm/msm: update for ARCH_MSM -> ARCH_QCOM drm/msm/hdmi: use gpio and HPD polling drm/msm/mdp5: fix crash in error/unload paths
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Daniel Vetter authored
The drm core shouldn't depend upon any helpers, and we make sure this doesn't accidentally happen by moving them into the helper-only drm_kms_helper.ko module. v2: Don't break the build for vmwgfx, spotted by Matt. v3: Unbreak the depency loop around CONFIG_FB (not actually a loop since it involves select). Reported by Chris. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Thomas Hellstrom <thellstrom@vmware.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Daniel Vetter authored
After the split-out of crtc locks from the big mode_config.mutex there's still two major areas it protects: - Various connector probe states, like connector->status, EDID properties, probed mode lists and similar information. - The links from connector->encoder and encoder->crtc and other modeset-relevant connector state (e.g. properties which control the panel fitter). The later is used by modeset operations. But they don't really care about the former since it's allowed to e.g. enable a disconnected VGA output or with a mode not in the probed list. Thus far this hasn't been a problem, but for the atomic modeset conversion Rob Clark needs to convert all modeset relevant locks into w/w locks. This is required because the order of acquisition is determined by how userspace supplies the atomic modeset data. This has run into troubles in the detect path since the i915 load detect code needs _both_ protections offered by the mode_config.mutex: It updates probe state and it needs to change the modeset configuration to enable the temporary load detect pipe. The big deal here is that for the probe/detect users of this lock a plain mutex fits best, but for atomic modesets we really want a w/w mutex. To fix this lets split out a new connection_mutex lock for the modeset relevant parts. For simplicity I've decided to only add one additional lock for all connector/encoder links and modeset configuration states. We have piles of different modeset objects in addition to those (like bridges or panels), so adding per-object locks would be much more effort. Also, we're guaranteed (at least for now) to do a full modeset if we need to acquire this lock. Which means that fine-grained locking is fairly irrelevant compared to the amount of time the full modeset will take. I've done a full audit, and there's just a few things that justify special focus: - Locking in drm_sysfs.c is almost completely absent. We should sprinkle mode_config.connection_mutex over this file a bit, but since it already lacks mode_config.mutex this patch wont make the situation any worse. This is material for a follow-up patch. - omap has a omap_framebuffer_flush function which walks the connector->encoder->crtc links and is called from many contexts. Some look like they don't acquire mode_config.mutex, so this is already racy. Again fixing this is material for a separate patch. - The radeon hot_plug function to retrain DP links looks at connector->dpms. Currently this happens without any locking, so is already racy. I think radeon_hotplug_work_func should gain mutex_lock/unlock calls for the mode_config.connection_mutex. - Same applies to i915's intel_dp_hot_plug. But again, this is already racy. - i915 load_detect code needs to acquire this lock. Which means the w/w dance due to Rob's work will be nicely contained to _just_ this function. I've added fixme comments everywhere where it looks suspicious but in the sysfs code. After a quick irc discussion with Dave Airlie it sounds like the lack of locking in there is due to sysfs cleanup fun at module unload. v1: original (only compile tested) v2: missing mutex_init(), etc (from Rob Clark) v3: i915 needs more care in the conversion: - Protect the edp pp logic with the connection_mutex. - Use connection_mutex in the backlight code due to get_pipe_from_connector. - Use drm_modeset_lock_all in suspend/resume paths. - Update lock checks in the overlay code. Cc: Alex Deucher <alexdeucher@gmail.com> Cc: Rob Clark <robdclark@gmail.com> Signed-off-by:
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Rob Clark authored
I find myself making this change locally whenever debugging FB reference counting. Which seems a bit silly. Signed-off-by:
David Herrmann <dh.herrmann@gmail.com>
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Rob Clark authored
Like range, but values are signed. Signed-off-by:
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Rob Clark authored
An object property is an id (idr) for a drm mode object. This will allow a property to be used set/get a framebuffer, CRTC, etc. Signed-off-by:
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Rob Clark authored
If we continue to use bitmask for type, we will quickly run out of room to add new types. Split this up so existing part of bitmask range continues to function as before, but reserve a chunk of the remaining space for an integer type-id. Wrap this all up in some type-check helpers to keep the backwards-compat uglyness contained. Signed-off-by:
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Rob Clark authored
Add a few more useful helpers to find mode objects. Signed-off-by:
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Jani Nikula authored
No longer used or needed as the structs have a name field. Acked-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Jani Nikula authored
Generated using semantic patch: @@ expression E; @@ - drm_get_encoder_name(E) + E->name Acked-by:
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Jani Nikula authored
Generated using semantic patches: @@ expression E; @@ - drm_get_encoder_name(&E) + E.name @@ expression E; @@ - drm_get_encoder_name(E) + E->name v2: Turn drm_get_encoder_name(&E) into E.name instead of &(E)->name. Acked-by:
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Jani Nikula authored
Generated using semantic patch: @@ expression E; @@ - drm_get_connector_name(E) + E->name [airlied: regenerated] Acked-by:
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Jani Nikula authored
Generated using semantic patch: @@ expression E; @@ - drm_get_connector_name(E) + E->name [airlied: regenerated] Acked-by:
Alex Deucher <alexander.deucher@amd.com> Acked-by:
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Jani Nikula authored
Generated using semantic patches: @@ expression E; @@ - drm_get_connector_name(&E) + E.name @@ expression E; @@ - drm_get_connector_name(E) + E->name v2: Turn drm_get_connector_name(&E) into E.name instead of &(E)->name. Acked-by:
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Jani Nikula authored
Generated using semantic patches: @@ expression E; @@ - drm_get_connector_name(&E) + E.name @@ expression E; @@ - drm_get_connector_name(E) + E->name v2: Turn drm_get_connector_name(&E) into E.name instead of &(E)->name. Acked-by:
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Jani Nikula authored
Generated using semantic patch: @@ expression E; @@ - drm_get_connector_name(E) + E->name Acked-by:
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David Mansfield authored
spice-server and downstream code expect that the primary surface will always have surface_id = 0, while in reality, once allocated, the surface_id in qxl.ko is NEVER 0. In a dual head environment, all monitors render portions of the primary surface. However, when the monitor config events are generated and sent, the primary surface is only mapped to the correct identifier (i.e. 0) for the primary head (where crtc index is 0). The fix is to look at the "primary" flag in the bo and always use id 0, irrespective of which head is being configured. [airlied: qxl hw really needs to be fixed to scanout surfaces] Signed-off-by: -
Christian König authored
Instead of trying to flip inside the vblank period when the buffer is idle, offload blocking for idle to a kernel thread and program the flip directly into the hardware. v2: add error handling, fix EBUSY handling v3: add proper exclusive_lock handling v4: update crtc->primary->fb when the flip actually happens Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Dave Airlie authored
This reverts commit 1aab5514. Apply the fixed up version instead.
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- 03 Jun, 2014 1 commit
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
Highlights: - GPUVM opimtizations - HDMI audio cleanups - Deep color HDMI support - more bug fixes, cleanups * 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux: (29 commits) drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color. drm/edid: Parse and handle HDMI deep color modes. drm/radeon: Limit hdmi deep color bit depth to 12 bpc. drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2) drm/radeon: fix pll setup for hdmi deep color (v7) drm/radeon: use hw cts/n values for deep color drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi drm/radeon/atom: fix dithering on certain panels drm/radeon: optimize CIK VM handling v2 drm/radeon: optimize SI VM handling drm/radeon: add define for flags used in R600+ GTT drm/radeon: rework page flip handling v3 drm/radeon: separate vblank and pflip crtc handling drm/radeon: split page flip and pending callback drm/radeon: remove drm_vblank_get|put from pflip handling drm/radeon: remove (pre|post)_page_flip callbacks drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices drm/radeon: fix typo in radeon_connector_is_dp12_capable() radeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770 vgaswitcheroo: switch the mux to the igp on power down when runpm is enabled ...
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- 02 Jun, 2014 7 commits
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Mario Kleiner authored
The Sony PVM-2541A OLED high precision color display supports both 10 bpc and 12 bpc hdmi deep color input, but its edid does not signal any deep color support. Add a quirk to force it being treated as a 12 bpc panel. Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by:
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Mario Kleiner authored
Check the HDMI cea block for deep color mode bits. If available, assign the highest supported bpc for a hdmi display, corresponding to the given deep color modes. Signed-off-by:
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Mario Kleiner authored
DCE-4/5/6 can't support more than 12 bpc deep color over hdmi, so clamp to 12 bpc when a hdmi deep color capable display is connected. This even makes sense on DCE-8+, which could do up to 16 bpc, as driving with more than 12 bpc would only waste video bandwidth as long as we don't support framebuffers with more than 12 bpc depth. On pre-DCE4 we clamp hdmi bit depth to 8 bpc, as those asics don't support hdmi deep color. Signed-off-by:
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Alex Deucher authored
Program HDMI_CONTROL to send general control packets for hdmi deep color mode signalling at every video frame if bpc > 8. This is only supported on evergreen / DCE-4 and later. v2: rebase Signed-off-by:
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Alex Deucher authored
Need to adjust the pll up for deep color modes. Additionally, the atom bpc defines were wrong in certain cases. v2: set the adjusted clock to the pll clock for hdmi deep color. This fixes display and audio issues with deep color as reported by Andy Furniss <adf.lists@gmail.com> v3: set crtc_clock as well v4: setcrtcinfo on the adjusted mode v5: just use the adjusted clock for setting the pll v6: only use the adjusted clock for hdmi v7: only DCE5 and DCE6 and bpc > 8 Signed-off-by: -
Alex Deucher authored
I'm not really sure how these should be calculated for deep color. The hw generated values seem to work. Signed-off-by: -
Alex Deucher authored
May fix display issues with non-HDMI displays. Signed-off-by:
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