- 24 May, 2017 40 commits
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Tom St Denis authored
Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Tom St Denis authored
Drop the function gmc_v6_0_init_compute_vmid() since it wasn't implemented and commented out. Signed-off-by:
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Tom St Denis authored
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Tom St Denis authored
Clean up coding style in gfx_v6_0_write_harvested_raster_configs() Signed-off-by:
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Tom St Denis authored
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Christian König authored
That line got missed during the merge. v2: fix vcn_v1_0_enc_ring_emit_vm_flush as well Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Christian König authored
That GFX9 needs a PDE in the registers is entirely GFX9 specific. Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
512 is enough for one PD entry on Vega10. Signed-off-by:
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Flora Cui authored
partial revert commit <6971d3d> - drm/amdgpu: cleanup logic in amdgpu_vm_flush Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
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Yintian Tao authored
If doorbell is used for wptr update, we also need to use it to initialize wptr to 0. Signed-off-by:
Yintian Tao <yttao@amd.com> Reviewed-by:
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Christian König authored
VM is mandatory for all hw amdgpu supports. So remove the leftovers to make it optionally. Signed-off-by:
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Chunming Zhou authored
The fence in dep_sync cannot be optimized. Signed-off-by:
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Ken Wang authored
Update gfx9 golden settings. Signed-off-by:
Ken Wang <Qingqing.Wang@amd.com> Acked-by:
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Chunming Zhou authored
If the vm is guilty of a GPU reset, skips all its jobs. Signed-off-by:
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Chunming Zhou authored
below ioctl will return -ENODEV: amdgpu_cs_ioctl amdgpu_cs_wait_ioctl amdgpu_cs_wait_fences_ioctl amdgpu_gem_va_ioctl amdgpu_info_ioctl v2: only for map and replace cases in amdgpu_gem_va_ioctl Signed-off-by:
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Chunming Zhou authored
backup first 64 byte of gart table as reset magic, check if magic is same after gpu hw reset. v2: use memcmp instead of manual innovation. Signed-off-by:
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Felix Kuehling authored
Clock index 0 is a valid index that is needed to restore the default graphics power profile. Use ~0 to indicate a failure to find a clock index. This fixes the clocks getting stuck in the compute power profile after running a compute application on Vega10. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Alex Deucher authored
Add support for parsing the gpu info table on raven. This is required to get the gpu config data for raven. Signed-off-by:
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Hawking Zhang authored
only mmhub will be invalidated during vcn dec/enc vm flush Signed-off-by:
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Hawking Zhang authored
This got missed due to differences in the trees when raven support was merged. Signed-off-by:
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kbuild test robot authored
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:75:42-43: WARNING: Use ARRAY_SIZE drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:466:22-23: WARNING: Use ARRAY_SIZE drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:468:22-23: WARNING: Use ARRAY_SIZE drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:470:20-21: WARNING: Use ARRAY_SIZE drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:473:22-23: WARNING: Use ARRAY_SIZE drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:475:21-22: WARNING: Use ARRAY_SIZE drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/rv_hwmgr.c:477:21-22: WARNING: Use ARRAY_SIZE Use ARRAY_SIZE instead of dividing sizeof array with sizeof an element Semantic patch information: This makes an effort to find cases where ARRAY_SIZE can be used such as where there is a division of sizeof the array by the sizeof its first element or by any indexed element or the element type. It replaces the division of the two sizeofs by ARRAY_SIZE. Generated by: scripts/coccinelle/misc/array_size.cocci CC: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Signed-off-by:
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Alex Deucher authored
Looks like a copy past issue. Reported-by:
Julia Lawall <julia.lawall@lip6.fr> Signed-off-by:
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Chunming Zhou authored
Add the RAVEN pci id. v2: add exp flag for now (Alex) Signed-off-by:
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Andrey Grodzovsky authored
v2: squash in some updates (Alex) Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Acked-by:
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Hawking Zhang authored
Add the ip block and enable powerplay on raven. Reviewed-by:
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Alex Deucher authored
By default VCN is powered down like SDMA, power it up/down on driver load/unload. [Rui: Fix to add the parameter 0 to un-gate VCN] v2 Acked-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Chunming Zhou authored
sdma is powered down by default in vbios, need to power up in driver init. Power it down again on driver tear down. Signed-off-by:
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Rex Zhu authored
hwmgr handles the GPU power state management. v2: squash in updates (Alex) Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
smumgr provides the interface for interacting with the smu firmware which handles power management. v2: squash in updates (Alex) Signed-off-by:
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Rex Zhu authored
defines clock dependencies for raven. Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
Headers define the driver/fw interface for smu10. v2: squash in updates (Alex) Signed-off-by:
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Huang Rui authored
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Huang Rui authored
Add sw controlled clockgating for VCN. Signed-off-by:
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Leo Liu authored
Based on new vcn firmware interface changes Signed-off-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Leo Liu authored
New firmware add psp header. Signed-off-by:
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
Update and enable the vcn encode IB test. Signed-off-by:
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Leo Liu authored
Wire up the callback and enable them. Signed-off-by:
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