- 16 Oct, 2023 21 commits
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Ville Syrjälä authored
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231012122442.15718-3-ville.syrjala@linux.intel.comReviewed-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by: -
Imre Deak authored
The previous patches converted all users of the DSC DPCD caps to look these up from the connector, so remove the version stored in intel_dp. A follow-up patchset will read out the MST connector specific capabilities in intel_dp_add_mst_connector() -> intel_dp_mst_read_decompression_port_dsc_caps(). v2: - Rebased on intel_edp_get_dsc_sink_cap() addition in the patchset. v3: - Rebased on read-out fix for eDP in the patchset. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1) Reviewed-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231011171606.2540078-3-imre.deak@intel.com
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_mst_mode_valid_ctx(). Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_dsc_compute_config(). Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_mode_valid(). Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_dsc_get_slice_count(). Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_dsc_supports_format(). Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_dsc_compute_params(). Reviewed-by:
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Imre Deak authored
intel_dp_sink_dsc_version_minor() only requires the DSC DPCD, so pass only this to the function. Reviewed-by:
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Imre Deak authored
intel_dp_source_dsc_version_minor() only requires the i915 pointer, so pass only this to the function. Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in drm_dp_dsc_sink_supported_input_bpcs(). Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_dsc_max_sink_compressed_bppx16(). Reviewed-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_supports_dsc(). Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_supports_fec(). Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_dsc_compute_max_bpp() instead of the version stored in the encoder. Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in i915_dsc_fec_support_show() instead of the version stored in the encoder. Atm the two are identical, but a follow-up patch will store the (MST) connector specific version in the connector. Reviewed-by:
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Imre Deak authored
Cache the i915 specific device and connector pointers in i915_dsc_fec_support_show(). v2: - s/Cahce/Cache typo in commit log. (Stan) Reviewed-by:
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Imre Deak authored
Similarly to eDP and SST-DP connectors read out the DSC capabilities for MST connectors as well. Atm these will match the root port's DSC caps and only used after a follow-up change enables the decompression for each stream separately (vs. the current way of enabling it only globally in the first branch device downstream of the root port). Reviewed-by:
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Imre Deak authored
In an MST topology the DSC capabilities are specific to each connector, retrieved either from the sink if it decompresses the stream, or from a branch device between the source and the sink in case this branch device does the decompression. Accordingly each connector needs to cache its own DSC DPCD and FEC capabilities, along with the AUX device through which the decompression can be enabled. This patch prepares for that by storing the capabilities and the DSC AUX device in the connector, for now these just matching the version stored in intel_dp. The follow-up patches will convert all users to look up these in the connector instead of intel_dp, after which the intel_dp copies are removed. v2: - Rebased on intel_edp_get_dsc_sink_cap() addition in previous patch. v3: - Rebased on read-out fix for eDP in previous patch. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1) Reviewed-by:
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Imre Deak authored
Check only the eDP or the DP specific DPCD revision depending on the sink type. Pass the corresponding revision to the function, which allows getting the DSC caps of a branch device (in an MST topology, which has its own DPCD and so DPCD revision). While at it use DP_DPCD_REV_14 instead of open coding it and for clarity add a separate function to read out the DSC capability on eDP. v2: - Use DP_DPCD_REV_14 instead of open coding it. (Stan) - Check EDP_DCPD_REV/DPCD_REV in a clearer way. (Ville) v3: - Fix the read-out for eDP in intel_dp_detect(). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2) Signed-off-by:
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- 13 Oct, 2023 4 commits
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Ville Syrjälä authored
With all the known issues sorted out we can start to use DSB to load the LUTs. Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
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Ville Syrjälä authored
The display engine does not snoop the caches so we should mark the DSB command buffer as I915_CACHE_NONE. i915_gem_object_create_internal() always gives us I915_CACHE_LLC on LLC platforms. And to make things 100% correct we should also clflush at the end, if necessary. Note that currently this is a non-issue as we always write the command buffer through a WC mapping, so a cache flush is not actually needed. But we might actually want to consider a WB mapping since we also end up reading from the command buffer (in the indexed reg write handling). Either that or we should do something else to avoid those reads (might actually be even more sensible on DGFX since we end up reading over PCIe). But we should measure the overhead first... Anyways, no real harm in adding the belts and suspenders here so that the code will work correctly regardless of how we map the buffer. If we do get a WC mapping (as we request) i915_gem_object_flush_map() will be a nop. Well, apart form a wmb() which may just flush the WC buffer a bit earlier than would otherwise happen (at the latest the mmio accesses would trigger the WC flush). Signed-off-by:
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Ville Syrjälä authored
Using system memory for the DSB command buffer doesn't appear to work. On DG2 it seems like the hardware internally replaces the actual memory reads with zeroes, and so we end up executing a bunch of NOOPs instead of whatever commands we put in the buffer. To determine that I measured the time it takes to execute the instructions, and the results are always more or less consistent with executing a buffer full of NOOPs from local memory. Another theory I considered was some kind of cache coherency issue. Looks like i915_gem_object_pin_map_unlocked() will in fact give you a WB mapping for system memory on DGFX regardless of what mapping mode was requested (WC in case of the DSB code). But clflush did not change the behaviour at all, so that theory seems moot. On DG1 it looks like the hardware might actually be fetching data from system memory as the logs indicate that we just get underruns. But that is equally bad, so doesn't look like we can really use system memory on DG1 either. Thus always allocate the DSB command buffer from local memory on discrete GPUs. Signed-off-by:
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Mika Kahola authored
Watchdog timers for Lunarlake HW were removed for PSR/PSR2 The patch removes the use of these timers from the driver code. BSpec: 69895 v2: Reword commit message (Ville) Drop HPD mask from LNL (Ville) Revise masking logic (Jouni) v3: Revise commit message (Ville) Revert HPD mask removal as irrelevant for this patch (Ville) Signed-off-by:Mika Kahola <mika.kahola@intel.com> Reviewed-by:
Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
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- 12 Oct, 2023 8 commits
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Shekhar Chauhan authored
Add recently added PCI IDs for DG2 BSpec: 44477 Signed-off-by:
Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Hans de Goede authored
Add some debug logging to mipi_exec_i2c, to make debugging various issues seen with it easier. Changes in v2: - Drop unnecessary __func__ drm_dbg_kms() argument Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Acked-by:
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Hans de Goede authored
On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 issues with the backlight on/off MIPI sequences: 1. The backlight on sequence has an I2C MIPI sequence element which uses bus 0, but there is a bogus I2cSerialBus resource under the GPU in the DSDT which causes i2c_acpi_find_adapter() to pick the wrong bus. 2. There is no backlight off sequence, causing the backlight to stay on. Add a DMI quirk fixing both issues. v2: - Add Closes tag to gitlab issue with drm.debug=0xe, VBT info Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9380Signed-off-by:
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Hans de Goede authored
drm/i915/vlv_dsi: Add DMI quirk for wrong I2C bus and panel size on Lenovo Yoga Tablet 2 series (v3) On the Lenovo Yoga Tablet 2 830 / 1050 there are 2 problems: 1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7 which under Linux become bus 0 - 6. And the MIPI sequence reference to bus 3 is indented for I2C3 which is bus 2 under Linux. This leads to errors like these: [ 178.244049] i2c_designware 80860F41:03: controller timed out [ 178.245703] i915 0000:00:02.0: [drm] *ERROR* Failed to xfer payload of size (1) to reg (169) There are 3 timeouts when the panel is on, delaying waking up the screen on a key press by 3 seconds. Note mipi_exec_i2c() cannot just subtract 1 from the bus given in the I2C MIPI sequence element. Since on other devices the I2C bus-numbers used in the MIPI sequences do actually start at 0. 2. width_/height_mm contain a bogus 192mm x 120mm size. This is especially a problem on the 8" 830 version which uses a 10:16 portrait screen where as the bogus size is 16:10. Add a DMI quirk to override the I2C bus and the panel size with the correct values. Note both the 10" 1050 models as well as the 8" 830 models use the same mainboard and thus the same DMI strings. The 10" 1050 uses a 1920x1200 landscape screen, where as the 8" 830 uses a 1200x1920 portrait screen, so the quirk handling uses the display resolution to detect the model. v2: - Also override i2c_bus_num to fix mipi_exec_i2c() timeouts v3: - Add Closes tag to gitlab issue with drm.debug=0xe, VBT info Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9379Reviewed-by:
Javier Martinez Canillas <javierm@redhat.com> Signed-off-by:
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Hans de Goede authored
Vtotal is wrong in the BIOS supplied modeline for the DSI panel on the Asus TF103C leading to the last line of the display being shown as the first line. Original: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 820 0x8 0xa Fixed: "1280x800": 60 67700 1280 1312 1328 1376 800 808 812 816 0x8 0xa The factory installed Android has a hardcoded modeline in its kernel, causing it to not suffer from this BIOS bug; and the Android boot-splash which uses the EFI FB which does have this bug has the last line all black causing the bug to not be visible. This commit introduces a generic DMI based quirk mechanism to vlv_dsi for doing various fixups, and uses this to correct the modeline. v2: - s/mode_fixup/dmi_quirk/ to make the new DMI quirk mechanism more generic - Add a comment with the old and new modelines to the patch and commit msg v3: - Add Closes tag to gitlab issue with drm.debug=0xe, VBT info Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9381Reviewed-by:
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Arun R Murthy authored
By default fastboot is enabled on all Display 9+ platforms and disabled on older platforms. Its not necessary to retain this as a module parameter. Signed-off-by:
Arun R Murthy <arun.r.murthy@intel.com> Acked-by:
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Suraj Kandpal authored
Create a new file intel_hdcp_gsc_message that contain functions which fill the hdcp messages we send to gsc cs this refactor will help us reuse code for Xe later on --v2 -add the missed file for proper build --v3 -use forward declarations instead of #includes [Jani] --v4 -move linux/err.h to intel_hdcp_gsc_message.c from intel_hdcp_gsc_message.h [Jani] --v5 -move linux include on top of drm includes [Uma] Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by:
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Suraj Kandpal authored
Move checks for gsc components required for HDCP 2.2 to work into intel_hdcp_gsc.c. This will also help with XE refactor on HDCP's side. Signed-off-by:
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- 11 Oct, 2023 7 commits
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Suraj Kandpal authored
Even though there is no leaking of resource here lets just use the correct method to free crtc_state Signed-off-by:
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Suraj Kandpal authored
intel_encoder_current_mode() seems to leak some resource because it uses kfree instead of intel_crtc_destroy_state let us fix that. Signed-off-by:
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Jani Nikula authored
We enable a bunch more compiler warnings than the kernel defaults. However, they've drifted to become a unique set of warnings, and have increasingly fallen behind from the W=1 set. Align with the W=1 warnings from scripts/Makefile.extrawarn for clarity, by copy-pasting them with s/KBUILD_CFLAGS/subdir-ccflags-y/ to make it easier to compare in the future. Some of the -Wextra warnings do need to be disabled, just like in Makefile.extrawarn, but take care to not disable them for W=2 or W=3 builds, depending on the warning. v2: Add back some -Wextra warning disables (Nathan) Cc: Arnd Bergmann <arnd@arndb.de> Cc: Nick Desaulniers <ndesaulniers@google.com> Cc: Nathan Chancellor <nathan@kernel.org> Cc: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by:
Nathan Chancellor <nathan@kernel.org> Reviewed-by:
Masahiro Yamada <masahiroy@kernel.org> [Final s/KBUILD_CFLAGS/subdir-ccflags-y/ fix while applying] Signed-off-by:
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Jani Nikula authored
The kernel top level Makefile, and recently scripts/Makefile.extrawarn, have included -Wall, and the disables -Wno-format-security and $(call cc-disable-warning,frame-address,) for a very long time. They're redundant in our local subdir-ccflags-y and can be dropped. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Nick Desaulniers <ndesaulniers@google.com> Cc: Nathan Chancellor <nathan@kernel.org> Cc: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by:
Nick Desaulniers <ndesaulniers@google.com> Reviewed-by:
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Khaled Almahallawy authored
Currently, with MFD/pin assignment D, the driver clears the pipe reset bit of lane 1 which is not owned by display. This causes the display to block S0iX. By not clearing this bit for lane 1 and keeping whatever default, S0ix started to work. This is already what the driver does at the end of the phy lane reset sequence (Step#8) Bspec: 65451 Fixes: 619a06db ("drm/i915/mtl: Reset only one lane in case of MFD") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by:
Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231005001310.154396-1-khaled.almahallawy@intel.com
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Jani Nikula authored
Structs intel_gvt_irq_info and intel_gvt_irq_map are not used outside of interrupt.c. Hide them, and reduce includes. Signed-off-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230926121904.499888-4-jani.nikula@intel.com
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Jani Nikula authored
struct engine_mmio is not used outside of mmio_context.c. Hide it, and reduce includes. Signed-off-by:
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