- 13 Sep, 2012 4 commits
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Laxman Dewangan authored
Add connection name "div-clk" for the i2c clock entry. Signed-off-by:
Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Laxman Dewangan authored
Tegra's i2c controller require two clock sources named as div_clk and fast_clk. This change make sure that driver pass the correct clock's name when it acquires clock handle. Also change the variable name to reflect the correct clock handles. Signed-off-by:
Laxman Dewangan <ldewangan@nvidia.com> Acked-by:
Wolfram Sang <w.sang@pengutronix.de> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Laxman Dewangan authored
Tegra's i2c controller require two clock sources named as div-clk and fast-clk for proper operation. Currently, the entry of fast-clk is missing in tegra30 clock table and it is incorrectly named in the tegra20 clock table. Adds aliases to enable lookups for "fast-clk" to succeed. A later patch will remove the incorrectly named clock, once the driver is modified to use the new name. Signed-off-by:
Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Clockevent's frequency is changed upon cpufreq change notification. It fetches local timer's rate to update the clockevent frequency. This patch adds local timer clock for Tegra20. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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- 11 Sep, 2012 2 commits
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Stephen Warren authored
When changing a PLL's rate, it must have no active children. The CPU clock cannot be stopped, and CPU clock's divider is not used. The old clock driver used to handle this by internally reparenting the CPU clock onto a different PLL when changing the CPU clock rate. However, the new common-clock based clock driver does not do this, and probably cannot do this due to the locking issues it would cause. To solve this, have the Tegra cpufreq driver explicitly perform the reparenting operations itself. This is probably reasonable anyway, since such reparenting is somewhat a matter of policy (e.g. which alternate clock source to use, whether to leave the CPU clock a child of the alternate clock source if it's running at the desired rate), and hence is something more appropriate for the cpufreq driver than the core clock driver anyway. Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
32-bit math isn't enough when e.g. *prate=12000000, and sel->n=1000. Use 64-bit math to prevent this. Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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- 07 Sep, 2012 1 commit
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Prashant Gaikwad authored
Warnings were generated because following commit changed data type for address pointer 195bbca ARM: 7500/1: io: avoid writeback addressing modes for __raw_ accessors arch/arm/mach-tegra/tegra30_clocks.c: In function 'clk_measure_input_freq': arch/arm/mach-tegra/tegra30_clocks.c:418:2: warning: passing argument 2 of '__raw_writel' makes pointer from integer without a cast .../arch/arm/include/asm/io.h:88:20: note: expected 'volatile void *' but argument is of type 'unsigned int Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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- 06 Sep, 2012 11 commits
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Stephen Warren authored
tegra_time is a struct sys_timer, not a struct clk, so can't be included in an array of struct clk *. Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
It should use tegra30_audio_sync_clk_ops for tegra30. It will cause the tegra30 use the wrong audio_sync_clk_ops when build a kernel with a tegra20 and tegra30 both supported kernel. And building error when a tegra30-only kernel. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
Currently the tegra20 and tegra30 share the same symbol for tegra_clk_32k_ops. This will cause a compile error when building a tegra20-only kernel image. Add tegra_clk_32k_ops for tegra20 and modify tegra30_clk_32k_ops for tegra30. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Remove Tegra legacy clock framework code. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
This patch converts tegra clock code to generic clock framework in following way: - Implement clk_ops as required by generic clk framework. (tegraXX_clocks.c) - Use platform specific struct clk_tegra in clk_ops implementation instead of struct clk. - Initialize all clock data statically. (tegraXX_clocks_data.c) Legacy framework did not have recalc_rate and is_enabled functions. Implemented these functions. Removed init function. It's functionality is splitted into recalc_rate and is_enabled. Static initialization is used since slab is not up in .init_early and clock is needed to be initialized before clockevent/clocksource initialization. Macros redefined for clk_tegra. Also, single struct clk_tegra is used for all type of clocks (PLL, peripheral etc.). This is to move quickly to generic common clock framework so that other dependent features will not be blocked (such as DT binding). Enabling COMMON_CLOCK config moved to ARCH_TEGRA since it is enabled for both Tegra20 and Tegra30. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add Tegra platform specific clock structure clk_tegra and some helper functions for generic clock framework. struct clk_tegra is the single strcture used for all types of clocks. reset and cfg_ex ops moved to clk_tegra from clk_ops. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Make the name consistent with other files. s/tegra2/tegra20 Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Move clock initialization data to separate file. This is required for migrating to generic clock framework if static initialization is used. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Move clock initialization data to separate file. This is required for migrating to generic clock framework if static initialization is used. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
A U16 divider can divide a clock by 1..64K. However, the range-check in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's downstream kernels already have the fixed range-check. In practice this is a problem on Whistler's I2C bus, which uses a bus clock rate of 100KHz (rather than the more common 400KHz on Tegra boards), which requires a HW module clock of 8*100KHz. The parent clock is 216MHz, leading to a desired divider of 270. Prior to conversion to the common clock framework, this range error was somehow ignored/irrelevant and caused no problems. However, the common clock framework evidently has more rigorous error-checking, so this failure causes the I2C bus to fail to operate correctly. Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
Some boards use UART D for the main serial console, and some use UART A. UART D's clock is listed in board-dt-tegra20.c's clock table, whereas UART A's clock is not. This causes the clock code to think UART A's clock is unsed. The common clock framework turns off unused clocks at boot time. This makes the kernel appear to hang. Add UART A's clock into the clock table to prevent this. Eventually, this requirement should be handled by the UART driver, and/or properties in a board-specific device tree file. Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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- 01 Sep, 2012 5 commits
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Linus Torvalds authored
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John Stultz authored
Andreas Bombe reported that the added ktime_t overflow checking added to timespec_valid in commit 4e8b1452 ("time: Improve sanity checking of timekeeping inputs") was causing problems with X.org because it caused timeouts larger then KTIME_T to be invalid. Previously, these large timeouts would be clamped to KTIME_MAX and would never expire, which is valid. This patch splits the ktime_t overflow checking into a new timespec_valid_strict function, and converts the timekeeping codes internal checking to use this more strict function. Reported-and-tested-by:
Andreas Bombe <aeb@debian.org> Cc: Zhouping Liu <zliu@redhat.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Prarit Bhargava <prarit@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org Signed-off-by:
John Stultz <john.stultz@linaro.org> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds authored
Pull KVM bugfixes from Marcelo Tosatti. * git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: x86: fix KVM_GET_MSR for PV EOI kvm: Fix nonsense handling of compat ioctl
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git://git.kernel.org/pub/scm/linux/kernel/git/jejb/parisc-2.6Linus Torvalds authored
Pull PARISC fixes from James Bottomley: "This is a set of two bug fixes. One is the ATOMIC problem which is now causing a compile failure in certain situations. The other is mishandling of PER_LINUX32 which may also cause user visible effects. Signed-off-by: James Bottomley <JBottomley@Parallels.com>" * tag 'parisc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/parisc-2.6: [PARISC] fix personality flag check in copy_thread() [PARISC] Redefine ATOMIC_INIT and ATOMIC64_INIT to drop the casts
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git://git.kernel.org/pub/scm/linux/kernel/git/s390/linuxLinus Torvalds authored
Pull s390 fixes from Martin Schwidefsky: "A couple of s390 bug fixes for 3.5-rc4" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: s390/32: Don't clobber personality flags on exec s390/smp: add missing smp_store_status() for !SMP s390/dasd: fix ioctl return value s390: Always use "long" for ssize_t to match size_t
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- 30 Aug, 2012 5 commits
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git://people.freedesktop.org/~airlied/linuxLinus Torvalds authored
Pull drm fixes from Dave Airlie: "A bunch of scattered fixes ati/intel/nouveau, couple of core ones, nothing too shocking or different." * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm: Add EDID_QUIRK_FORCE_REDUCED_BLANKING for ASUS VW222S gma500: Consider CRTC initially active. drm/radeon: fix dig encoder selection on DCE61 drm/radeon: fix double free in radeon_gpu_reset drm/radeon: force dma32 to fix regression rs4xx,rs6xx,rs740 drm/radeon: rework panel mode setup drm/radeon/atom: powergating fixes for DCE6 drm/radeon/atom: rework DIG modesetting on DCE3+ drm/radeon: don't disable plls that are in use by other crtcs drm/radeon: add proper checking of RESOLVE_BOX command for r600-r700 drm/radeon: initialize tracked CS state drm/radeon: fix reading CB_COLORn_MASK from the CS drm/nvc0/copy: check PUNITS to determine which copy engines are disabled i915: Quirk no_lvds on Gigabyte GA-D525TUD ITX motherboard drm/i915: Use the correct size of the GTT for placing the per-process entries drm: Check for invalid cursor flags drm: Initialize object type when using DRM_MODE() macro drm/i915: fix color order for BGR formats on IVB drm/i915: fix wrong order of parameters in port checking functions
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Heiko Carstens authored
In native 32 bit mode the personality flags were not correctly inherited. This is the s390 version of 59e4c3a2 "powerpc/32: Don't clobber personality flags on exec". Reported-by:
Mike Frysinger <vapier@gentoo.org> Signed-off-by:
Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by:
Martin Schwidefsky <schwidefsky@de.ibm.com>
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Paul Menzel authored
Connecting an ASUS VW222S [1] over VGA a garbled screen is shown with vertical stripes in the top half. In commit bc42aabc [2] commit bc42aabc Author: Adam Jackson <ajax@redhat.com> Date: Wed May 23 16:26:54 2012 -0400 drm/edid/quirks: ViewSonic VA2026w Adam Jackson added the quirk `EDID_QUIRK_FORCE_REDUCED_BLANKING` which is also needed for this ASUS monitor. All log files and output from `xrandr` is included in the referenced Bugzilla report #17629. Please note that this monitor only has a VGA (D-Sub) connector [1]. [1] http://www.asus.com/Display/LCD_Monitors/VW222S/ [2] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=commit;h=bc42aabc6a01b92b0f961d65671564e0e1cd7592 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=17629Signed-off-by:
Paul Menzel <paulepanter@users.sourceforge.net> Cc: <dri-devel@lists.freedesktop.org> Cc: Adam Jackson <ajax@redhat.com> Cc: Ian Pilcher <arequipeno@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
Alex writes: Highlights: - fix a gart regression on older IGP chips - more MSAA fixes - fix a double free in gpu reset code - modesetting fixes - trinity dig encoder fix. * 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: fix dig encoder selection on DCE61 drm/radeon: fix double free in radeon_gpu_reset drm/radeon: force dma32 to fix regression rs4xx,rs6xx,rs740 drm/radeon: rework panel mode setup drm/radeon/atom: powergating fixes for DCE6 drm/radeon/atom: rework DIG modesetting on DCE3+ drm/radeon: don't disable plls that are in use by other crtcs drm/radeon: add proper checking of RESOLVE_BOX command for r600-r700 drm/radeon: initialize tracked CS state drm/radeon: fix reading CB_COLORn_MASK from the CS
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Forest Bond authored
[this one ideally should make 3.6 - it fixes the very annoying mode setting bug] This causes the pipe to be forced off prior to initial mode set, which roughly mirrors the behavior of the i915 driver. It fixes initial mode setting on my Intel DN2800MT (Cedarview) board. Without it, mode setting triggers an out-of-range error from the monitor for most modes, but only on initial configuration (i.e. they can be configured successfully from userspace after that). Signed-off-by:
Forest Bond <forest.bond@rapidrollout.com> Signed-off-by:
Alan Cox <alan@linux.intel.com> Cc: stable <stable@vger.kernel.org> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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- 29 Aug, 2012 12 commits
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Alex Deucher authored
Was using the DCE41 code which was wrong. Fixes blank displays on a number of Trinity systems. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux-btrfsLinus Torvalds authored
Pull btrfs fixes from Chris Mason: "I've split out the big send/receive update from my last pull request and now have just the fixes in my for-linus branch. The send/recv branch will wander over to linux-next shortly though. The largest patches in this pull are Josef's patches to fix DIO locking problems and his patch to fix a crash during balance. They are both well tested. The rest are smaller fixes that we've had queued. The last rc came out while I was hacking new and exciting ways to recover from a misplaced rm -rf on my dev box, so these missed rc3." * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux-btrfs: (25 commits) Btrfs: fix that repair code is spuriously executed for transid failures Btrfs: fix ordered extent leak when failing to start a transaction Btrfs: fix a dio write regression Btrfs: fix deadlock with freeze and sync V2 Btrfs: revert checksum error statistic which can cause a BUG() Btrfs: remove superblock writing after fatal error Btrfs: allow delayed refs to be merged Btrfs: fix enospc problems when deleting a subvol Btrfs: fix wrong mtime and ctime when creating snapshots Btrfs: fix race in run_clustered_refs Btrfs: don't run __tree_mod_log_free_eb on leaves Btrfs: increase the size of the free space cache Btrfs: barrier before waitqueue_active Btrfs: fix deadlock in wait_for_more_refs btrfs: fix second lock in btrfs_delete_delayed_items() Btrfs: don't allocate a seperate csums array for direct reads Btrfs: do not strdup non existent strings Btrfs: do not use missing devices when showing devname Btrfs: fix that error value is changed by mistake Btrfs: lock extents as we map them in DIO ...
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git://www.linux-watchdog.org/linux-watchdogLinus Torvalds authored
Pull watchdog fixes from Wim Van Sebroeck: "This will fix a warning for watchdog-test.c and it will remove a duplicate include of delay.h" * git://www.linux-watchdog.org/linux-watchdog: watchdog: da9052: Remove duplicate inclusion of delay.h watchdog: fix watchdog-test.c build warning
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David Rientjes authored
cache_grow() can reenable irqs so the cpu (and node) can change, so ensure that we take list_lock on the correct nodelist. This fixes an issue with commit 072bb0aa ("mm: sl[au]b: add knowledge of PFMEMALLOC reserve pages") where list_lock for the wrong node was taken after growing the cache. Reported-and-tested-by:
Haggai Eran <haggaie@mellanox.com> Signed-off-by:
David Rientjes <rientjes@google.com> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Christian König authored
radeon_ring_restore is freeing the memory for the saved ring data. We need to remember that, otherwise we try to restore the ring data again on the next try. Additional to that it shouldn't try the reset infinitely if we have saved ring data. Signed-off-by:
Christian König <deathsimple@vodafone.de> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com>
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Jerome Glisse authored
It seems some of those IGP dislike non dma32 page despite what documentation says. Fix regression since we allowed non dma32 pages. It seems it only affect some revision of those IGP chips as we don't know which one just force dma32 for all of them. https://bugzilla.redhat.com/show_bug.cgi?id=785375Signed-off-by:
Jerome Glisse <jglisse@redhat.com> Cc: <stable@vger.kernel.org> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Adjust the panel mode setup to match the behavior of the vbios. Rather than checking for specific bridge chip ids, just check the eDP configuration register. This saves extra aux transactions and works across DP bridge chips without requiring additional per chip id checking. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Power gating is per crtc pair, but the powergating registers should be called individually. The hw handles power up/down properly. The pair is powered up if either crtc in the pair is powered up and the pair is not powered down until both crtcs in the pair are powered down. This simplifies programming and should save additional power as the previous code never actually power gated the crtc pair. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
The ordering is important and the current drm code wasn't cutting it for modern DIG encoders. We need to have information about crtc before setting up the encoders so I've shifted the ordering a bit. Probably we'll need a full rework akin to danvet's recent intel patchs. This patch fixes numerous issues with DP bridge chips and makes link training much more reliable. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
Some plls are shared for DP. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com>
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Marek Olšák authored
Checking of the second colorbuffer was skipped on r700, because CB_TARGET_MASK was 0xf. With r600, CB_TARGET_MASK is changed to 0xff, so we must set the number of samples of the second colorbuffer to 1 in order to pass the CS checker. The DRM version is bumped, because RESOLVE_BOX is always rejected without this fix on r600. Signed-off-by:
Marek Olšák <maraeo@gmail.com> Reviewed-by:
Jerome Glisse <jglisse@redhat.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Marek Olšák authored
This should help catch uninitialized registers and reject commands because of that. Signed-off-by:
Marek Olšák <maraeo@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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