- 01 Aug, 2014 9 commits
-
-
Hans de Goede authored
Don't complain about controllers without sg support if there are other reasons why uas cannot be used anyways. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-
Hans de Goede authored
Signed-off-by:
-
Hans de Goede authored
The 7023 product id is the generic product id for the Etron EJ168, it is not specific to the version found on the Asrock P67 motherboard. The same id is e.g. also used on Gigabyte motherboards and on no-name pci-e usb-3 addon cards. Signed-off-by:
-
Hans de Goede authored
Streams on the EJ168 do not work as they should. I've spend 2 days trying to get them to work, but without success. The first problem is that when ever you ring the stream-ring doorbell, the controller starts executing trbs at the beginning of the first ring segment, event if it ended somewhere else previously. This can be worked around by allowing enqueing only one td (not a problem with how streams are typically used) and then resetting our copies of the enqueueing en dequeueing pointers on a td completion to match what the controller seems to be doing. This way things seem to start working with uas and instead of being able to complete only the very first scsi command, the scsi core can probe the disk. But then things break later on when td-s get enqueued with more then one trb. The controller does seem to increase its dequeue pointer while executing a stream-ring (data transfer events I inserted for debugging do trigger). However execution seems to stop at the final normal trb of a multi trb td, even if there is a data transfer event inserted after the final trb. The first problem alone is a serious deviation from the spec, and esp. dealing with cancellation would have been very tricky if not outright impossible, but the second problem simply is a deal breaker altogether, so this patch simply disables streams. Note this will cause the usb-storage + uas driver pair to automatically switch to using usb-storage instead of uas on these devices, essentially reverting to the 3.14 and earlier behavior when uas was marked CONFIG_BROKEN. https://bugzilla.redhat.com/show_bug.cgi?id=1121288 https://bugzilla.kernel.org/show_bug.cgi?id=80101 Cc: stable@vger.kernel.org # 3.15 Signed-off-by:
-
Hans de Goede authored
Some jmicron uas chipsets act up (they disconnect from the bus) when sending more then 32 commands to them at once. Rather then building an ever growing list with usb-id based quirks for devices using this chipset, simply reduce the qdepth to 32 when connected over usb-2. 32 should be plenty to keep things close to maximum possible throughput on usb-2. Cc: stable@vger.kernel.org Tested-and-reported-by:
Laszlo T. <tlacix@gmail.com> Signed-off-by:
-
Julia Lawall authored
Correct typo in the name of the type given to sizeof. Because it is the size of a pointer that is wanted, the typo has no impact on compilation or execution. This problem was found using Coccinelle (http://coccinelle.lip6.fr/). The semantic patch used can be found in message 0 of this patch series. Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
-
James P Michels III authored
This patch adds a usb quirk to support devices with interupt endpoints and bInterval values expressed as microframes. The quirk causes the parse endpoint function to modify the reported bInterval to a standards conforming value. There is currently code in the endpoint parser that checks for bIntervals that are outside of the valid range (1-16 for USB 2+ high speed and super speed interupt endpoints). In this case, the code assumes the bInterval is being reported in 1ms frames. As well, the correction is only applied if the original bInterval value is out of the 1-16 range. With this quirk applied to the device, the bInterval will be accurately adjusted from microframes to an exponent. Signed-off-by:
James P Michels III <james.p.michels@gmail.com> Signed-off-by:
-
Patrick Riphagen authored
This adds support for new Xsens devices, using Xsens' own Vendor ID. Signed-off-by:
Patrick Riphagen <patrick.riphagen@xsens.com> Signed-off-by:
Frans Klaver <frans.klaver@xsens.com> Cc: Johan Hovold <johan@kernel.org> Cc: stable <stable@vger.kernel.org> Signed-off-by:
-
Patrick Riphagen authored
The converters are used in specific products. It can be useful to know which they are exactly. Signed-off-by:
-
- 22 Jul, 2014 31 commits
-
-
Greg Kroah-Hartman authored
Merge tag 'for_3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: for_3.17 Adds regulator support in PHY core. PHY core is modified to support representation of multi-phy PHY providers with each individual PHY as sub-node OF PHY provider node. New PHY drivers adapted to PHY framework (hix5hd2 SATA PHY, QCOM APQ8064 SATA PHY, QCOM IPQ806x SATA PHY, Berlin SATA PHY and MiPHY356x). Existing TI PIPE3 PHY can now be used for PCIe too. Includes misc fixes and cleanups.
-
Wei Yongjun authored
Fixes the following sparse warnings: drivers/usb/chipidea/debug.c:211:5: warning: symbol 'ci_otg_show' was not declared. Should it be static? drivers/usb/chipidea/debug.c:334:5: warning: symbol 'ci_registers_show' was not declared. Should it be static? Signed-off-by:
Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by:
Peter Chen <peter.chen@freescale.com> Signed-off-by:
-
Markus Pargmann authored
fsl,usbphy is no optional property. This patch moves it to the list of required properties. Signed-off-by:
Markus Pargmann <mpa@pengutronix.de> Signed-off-by:
-
Markus Pargmann authored
-ENODEV is interpreted by the generic driver probing function as a non-matching driver. This leads to a missing probe failure message. Also a missing USB PHY is more of an invalid configuration of the usb driver because it is necessary. This patch returns -EINVAL if devm_usb_get_phy_by_phandle() returned -ENODEV. Signed-off-by:
-
Amit Virdi authored
Section 4.4.7.2 "Interrupt Transfer Bandwidth Requirements" of the USB3.0 spec says: A zero-length data payload is a valid transfer and may be useful for some implementations. So, extend the logic of allowing URB_ZERO_PACKET to interrupt urbs too. Otherwise, the kernel throws warning of BOGUS transfer flags. Signed-off-by:
Amit Virdi <amit.virdi@st.com> Acked-by:
Alan Stern <stern@rowland.harvard.edu> Signed-off-by:
-
Pratyush Anand authored
Following sparse warnings were reported by kbuild test bot drivers/usb/misc/lvstest.c:314:28: sparse: incorrect type in assignment (different base types) drivers/usb/misc/lvstest.c:314:28: expected unsigned short [unsigned] [usertype] portchange drivers/usb/misc/lvstest.c:314:28: got restricted __le16 [usertype] wPortChange drivers/usb/misc/lvstest.c:332:40: sparse: restricted __le16 degrades to integer This patch fixes above warnings. Reported-by:
kbuild test robot <fengguang.wu@intel.com> Signed-off-by:
Pratyush Anand <pratyush.anand@st.com> Signed-off-by:
-
Jiang Liu authored
The assigned IRQ should be freed before calling pci_disable_device() when shutting down system, otherwise it will cause following warning. [ 568.879482] ------------[ cut here ]------------ [ 568.884236] WARNING: CPU: 1 PID: 3300 at /home/konrad/ssd/konrad/xtt-i386/bootstrap/linux-usb/fs/proc/generic.c:521 remove_proc_entry+0x165/0x170() [ 568.897846] remove_proc_entry: removing non-empty directory 'irq/16', leaking at least 'ohci_hcd:usb4' [ 568.907430] Modules linked in: dm_multipath dm_mod iscsi_boot_sysfs iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi libcrc32c crc32c_generic sg sd_mod crct10dif_generic crc_t10dif crct10dif_common radeon fbcon tileblit ttm font bitblit softcursor ata_generic ahci libahci drm_kms_helper skge r8169 libata mii scsi_mod wmi acpi_cpufreq [ 568.938539] CPU: 1 PID: 3300 Comm: init Tainted: G W 3.16.0-rc5upstream-01651-g03b9189 #1 [ 568.947946] Hardware name: ECS A780GM-A Ultra/A780GM-A Ultra, BIOS 080015 04/01/2010 [ 568.956008] 00000209 ed0f1cd0 c1617946 c175403c ed0f1d00 c1090c3f c1754084 ed0f1d2c [ 568.964068] 00000ce4 c175403c 00000209 c11f22a5 c11f22a5 f755e8c0 ed0f1d78 f755e90d [ 568.972128] ed0f1d18 c1090cde 00000009 ed0f1d10 c1754084 ed0f1d2c ed0f1d60 c11f22a5 [ 568.980194] Call Trace: [ 568.982715] [<c1617946>] dump_stack+0x48/0x60 [ 568.987294] [<c1090c3f>] warn_slowpath_common+0x7f/0xa0 [ 569.003887] [<c1090cde>] warn_slowpath_fmt+0x2e/0x30 [ 569.009092] [<c11f22a5>] remove_proc_entry+0x165/0x170 [ 569.014476] [<c10da6ca>] unregister_irq_proc+0xaa/0xc0 [ 569.019858] [<c10d582f>] free_desc+0x1f/0x60 [ 569.024346] [<c10d58aa>] irq_free_descs+0x3a/0x80 [ 569.029283] [<c10d9e9d>] irq_dispose_mapping+0x2d/0x50 [ 569.034666] [<c1078fd3>] mp_unmap_irq+0x73/0xa0 [ 569.039423] [<c107196b>] acpi_unregister_gsi_ioapic+0x2b/0x40 [ 569.045431] [<c107180f>] acpi_unregister_gsi+0xf/0x20 [ 569.050725] [<c1339cad>] acpi_pci_irq_disable+0x4b/0x50 [ 569.056196] [<c14daa38>] pcibios_disable_device+0x18/0x20 [ 569.061848] [<c130123d>] do_pci_disable_device+0x4d/0x60 [ 569.067410] [<c13012b7>] pci_disable_device+0x47/0xb0 [ 569.077814] [<c14800b1>] usb_hcd_pci_shutdown+0x31/0x40 [ 569.083285] [<c1304b19>] pci_device_shutdown+0x19/0x50 [ 569.088667] [<c13fda64>] device_shutdown+0x14/0x120 [ 569.093777] [<c10ac29d>] kernel_restart_prepare+0x2d/0x30 [ 569.099429] [<c10ac41e>] kernel_restart+0xe/0x60 [ 569.109028] [<c10ac611>] SYSC_reboot+0x191/0x220 [ 569.159269] [<c10ac6ba>] SyS_reboot+0x1a/0x20 [ 569.163843] [<c161c718>] sysenter_do_call+0x12/0x16 [ 569.168951] ---[ end trace ccc1ec4471c289c9 ]--- Tested-by:
Aaron Lu <aaron.lu@intel.com> Signed-off-by:
Jiang Liu <jiang.liu@linux.intel.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
-
Lee Jones authored
This has the added advantages of being able to enable/disable each of the channels as simply as enabling/disabling the DT node. Suggested-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
-
Lee Jones authored
The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration. Acked-by:
Mark Rutland <mark.rutland@arm.com> Signed-off-by:
Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by:
-
Lee Jones authored
The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration. Acked-by:
-
Kumar Gala authored
Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on the IPQ806x family of SoCs. Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
-
Kumar Gala authored
Add a PHY driver for uses with AHCI based SATA controller driver on the IPQ806x family of SoCs. Signed-off-by:
-
Srinivas Kandagatla authored
This patch fixes a possible timeout in poll loop without actually checking the register before return. In theory the there is a possibility of loop being scheduled after a long lock/delay, which would then force the loop to exit without actually checking the register. Reported-by:
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
-
Kishon Vijay Abraham I authored
In case of multi-phy PHY providers, each PHY should be modeled as a sub node of the PHY provider. Then each PHY will have a different node pointer (node pointer of sub node) than that of PHY provider. Added this provision in the PHY core. Also fixed all drivers to use the updated API. Signed-off-by:
-
Kishon Vijay Abraham I authored
Fixed of_phy_provider_lookup to return 'phy_provider' if _of_phy_get passes the node pointer of the sub-node of phy provider node. This is needed when phy provider implements multiple PHYs and each PHY is modelled as the sub-node of PHY provider device node. Signed-off-by:
-
Antoine Ténart authored
The Berlin SATA PHY drives the PHY related to the SATA interface. Add the corresponding documentation. Signed-off-by:
Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by:
-
Antoine Ténart authored
The Berlin SoC has a two SATA ports. Add a PHY driver to handle them. The mode selection can let us think this PHY can be configured to fit other purposes. But there are reasons to think the SATA mode will be the only one usable: the PHY registers are only accessible indirectly through two registers in the SATA range, the PHY seems to be integrated and no information tells us the contrary. For these reasons, make the driver a SATA PHY driver. Signed-off-by:
-
Andrew Lunn authored
mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu. Depend on MACH_KIRKWOOD, which will be set when these SoCs are built as part of mach-mvebv. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
-
Srinivas Kandagatla authored
This patch adds binding spec for Qualcomm AP8064 SATA PHY. Signed-off-by:
Kiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by:
-
Srinivas Kandagatla authored
Add a PHY driver for uses with AHCI based SATA controller driver on the APQ8064 family of SoCs. This patch is a forward port from Qualcomm's v3.4 andriod kernel. Tested on IFC6410 board. CC: Sujit Reddy Thumma <sthumma@codeaurora.org> Tested-by:
-
Sachin Kamat authored
USB DWC3 driver on Exynos platform does not work without its corresponding phy driver. Hence make the PHY driver depend on Exynos DWC3 driver and default it to yes to make things easier for the end user. Signed-off-by:
Sachin Kamat <sachin.kamat@samsung.com> Reviewed-by:
Jingoo Han <jg1.han@samsung.com> Tested-by:
Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by:
-
Sachin Kamat authored
Since the USB 2.0 PHYs are required with EHCI/OHCI USB drivers and USB gadget controller supported by the DWC2 gadget driver, make it depend on them and default to ARCH_EXYNOS as they are meant for Exynos platforms. Also, make the sub-drivers silent options enabling them based on the SoC platforms that they are meant to work with. This will make life easier for end users who do not have any way knowing the dependencies. Signed-off-by:
-
Roger Quadros authored
phy-supply is a phandle to the regulator that provides power to the PHY. This regulator is managed during the PHY power on/off sequence by the phy core driver. Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
-
Roger Quadros authored
Some PHYs can be powered by an external power regulator. e.g. USB_HS PHY on DRA7 SoC. Make the PHY core support a power regulator. Signed-off-by:
-
Marek Szyprowski authored
This patch adds support for Exynos3250 SoC to Exynos2USB PHY driver. Although Exynos3250 has only one device phy interface, the register layout and all operations that are required to get it enabled are almost same as on Exynos4x12. The only different is one more register (REFCLKSEL) which need to be set and lack of MODE SWITCH register. Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
-
Jiancheng Xue authored
Add hix5hd2-sata-phy driver on Hisilicon hix5hd2 soc. Signed-off-by:
Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by:
Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by:
-
Jiancheng Xue authored
Add necessary binding documentation SATA PHY on Hisilicon hix5hd2 soc. Signed-off-by:
-
Kishon Vijay Abraham I authored
8-bit delay value (0xF1) is required for GEN2 devices to be enumerated consistently. Added an API to be called from PHY drivers to set this delay value and called it from PIPE3 driver to set the delay value. Signed-off-by:
-
Kishon Vijay Abraham I authored
PCIe PHY uses an external pll instead of the internal pll used by SATA and USB3. So added support in pipe3 PHY to use external pll. Signed-off-by:
-
Kamil Debski authored
The Exynos4412 USB 2.0 PHY hardware differs from the description provided in the documentation. Some register bits have different function. This patch fixes the defines of register bits and changes the way how phys are powered on and off. Signed-off-by:
Kamil Debski <k.debski@samsung.com> Tested-by:
Daniel Drake <drake@endlessm.com> Tested-by:
-
Jingoo Han authored
Make local functions static, because these are used only in this file. Signed-off-by:
-
