1. 31 Jan, 2018 3 commits
    • Christoffer Dall's avatar
      KVM: arm/arm64: Fixup userspace irqchip static key optimization · cd15d205
      Christoffer Dall authored
      When I introduced a static key to avoid work in the critical path for
      userspace irqchips which is very rarely used, I accidentally messed up
      my logic and used && where I should have used ||, because the point was
      to short-circuit the evaluation in case userspace irqchips weren't even
      in use.
      
      This fixes an issue when running in-kernel irqchip VMs alongside
      userspace irqchip VMs.
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Fixes: c44c232ee2d3 ("KVM: arm/arm64: Avoid work when userspace iqchips are not used")
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      cd15d205
    • Christoffer Dall's avatar
      KVM: arm/arm64: Fix userspace_irqchip_in_use counting · f1d7231c
      Christoffer Dall authored
      We were not decrementing the static key count in the right location.
      kvm_arch_vcpu_destroy() is only called to clean up after a failed
      VCPU create attempt, whereas kvm_arch_vcpu_free() is called on teardown
      of the VM as well.  Move the static key decrement call to
      kvm_arch_vcpu_free().
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      f1d7231c
    • Christoffer Dall's avatar
      KVM: arm/arm64: Fix incorrect timer_is_pending logic · 13e59ece
      Christoffer Dall authored
      After the recently introduced support for level-triggered mapped
      interrupt, I accidentally left the VCPU thread busily going back and
      forward between the guest and the hypervisor whenever the guest was
      blocking, because I would always incorrectly report that a timer
      interrupt was pending.
      
      This is because the timer->irq.level field is not valid for mapped
      interrupts, where we offload the level state to the hardware, and as a
      result this field is always true.
      
      Luckily the problem can be relatively easily solved by not checking the
      cached signal state of either timer in kvm_timer_should_fire() but
      instead compute the timer state on the fly, which we do already if the
      cached signal state wasn't high.  In fact, the only reason for checking
      the cached signal state was a tiny optimization which would only be
      potentially faster when the polling loop detects a pending timer
      interrupt, which is quite unlikely.
      
      Instead of duplicating the logic from kvm_arch_timer_handler(), we
      enlighten kvm_timer_should_fire() to report something valid when the
      timer state is loaded onto the hardware.  We can then call this from
      kvm_arch_timer_handler() as well and avoid the call to
      __timer_snapshot_state() in kvm_arch_timer_get_input_level().
      Reported-by: default avatarTomasz Nowicki <tn@semihalf.com>
      Tested-by: default avatarTomasz Nowicki <tn@semihalf.com>
      Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      13e59ece
  2. 23 Jan, 2018 2 commits
  3. 17 Jan, 2018 1 commit
  4. 09 Jan, 2018 1 commit
  5. 08 Jan, 2018 10 commits
  6. 02 Jan, 2018 11 commits
    • Christoffer Dall's avatar
      KVM: arm/arm64: Delete outdated forwarded irq documentation · e5a2cfb4
      Christoffer Dall authored
      The reason I added this documentation originally was that the concept of
      "never taking the interrupt", but just use the timer to generate an exit
      from the guest, was confusing to most, and we had to explain it several
      times over.  But as we can clearly see, we've failed to update the
      documentation as the code has evolved, and people who need to understand
      these details are probably better off reading the code.
      
      Let's lighten our maintenance burden slightly and just get rid of this.
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      e5a2cfb4
    • Christoffer Dall's avatar
      KVM: arm/arm64: Avoid work when userspace iqchips are not used · 61bbe380
      Christoffer Dall authored
      We currently check if the VM has a userspace irqchip in several places
      along the critical path, and if so, we do some work which is only
      required for having an irqchip in userspace.  This is unfortunate, as we
      could avoid doing any work entirely, if we didn't have to support
      irqchip in userspace.
      
      Realizing the userspace irqchip on ARM is mostly a developer or hobby
      feature, and is unlikely to be used in servers or other scenarios where
      performance is a priority, we can use a refcounted static key to only
      check the irqchip configuration when we have at least one VM that uses
      an irqchip in userspace.
      Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      61bbe380
    • Christoffer Dall's avatar
      KVM: arm/arm64: Provide a get_input_level for the arch timer · 4c60e360
      Christoffer Dall authored
      The VGIC can now support the life-cycle of mapped level-triggered
      interrupts, and we no longer have to read back the timer state on every
      exit from the VM if we had an asserted timer interrupt signal, because
      the VGIC already knows if we hit the unlikely case where the guest
      disables the timer without ACKing the virtual timer interrupt.
      
      This means we rework a bit of the code to factor out the functionality
      to snapshot the timer state from vtimer_save_state(), and we can reuse
      this functionality in the sync path when we have an irqchip in
      userspace, and also to support our implementation of the
      get_input_level() function for the timer.
      
      This change also means that we can no longer rely on the timer's view of
      the interrupt line to set the active state, because we no longer
      maintain this state for mapped interrupts when exiting from the guest.
      Instead, we only set the active state if the virtual interrupt is
      active, and otherwise we simply let the timer fire again and raise the
      virtual interrupt from the ISR.
      Reviewed-by: default avatarEric Auger <eric.auger@redhat.com>
      Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      4c60e360
    • Christoffer Dall's avatar
      KVM: arm/arm64: Support VGIC dist pend/active changes for mapped IRQs · df635c5b
      Christoffer Dall authored
      For mapped IRQs (with the HW bit set in the LR) we have to follow some
      rules of the architecture.  One of these rules is that VM must not be
      allowed to deactivate a virtual interrupt with the HW bit set unless the
      physical interrupt is also active.
      
      This works fine when injecting mapped interrupts, because we leave it up
      to the injector to either set EOImode==1 or manually set the active
      state of the physical interrupt.
      
      However, the guest can set virtual interrupt to be pending or active by
      writing to the virtual distributor, which could lead to deactivating a
      virtual interrupt with the HW bit set without the physical interrupt
      being active.
      
      We could set the physical interrupt to active whenever we are about to
      enter the VM with a HW interrupt either pending or active, but that
      would be really slow, especially on GICv2.  So we take the long way
      around and do the hard work when needed, which is expected to be
      extremely rare.
      
      When the VM sets the pending state for a HW interrupt on the virtual
      distributor we set the active state on the physical distributor, because
      the virtual interrupt can become active and then the guest can
      deactivate it.
      
      When the VM clears the pending state we also clear it on the physical
      side, because the injector might otherwise raise the interrupt.  We also
      clear the physical active state when the virtual interrupt is not
      active, since otherwise a SPEND/CPEND sequence from the guest would
      prevent signaling of future interrupts.
      
      Changing the state of mapped interrupts from userspace is not supported,
      and it's expected that userspace unmaps devices from VFIO before
      attempting to set the interrupt state, because the interrupt state is
      driven by hardware.
      Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Reviewed-by: default avatarEric Auger <eric.auger@redhat.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      df635c5b
    • Christoffer Dall's avatar
      KVM: arm/arm64: Support a vgic interrupt line level sample function · b6909a65
      Christoffer Dall authored
      The GIC sometimes need to sample the physical line of a mapped
      interrupt.  As we know this to be notoriously slow, provide a callback
      function for devices (such as the timer) which can do this much faster
      than talking to the distributor, for example by comparing a few
      in-memory values.  Fall back to the good old method of poking the
      physical GIC if no callback is provided.
      Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Reviewed-by: default avatarEric Auger <eric.auger@redhat.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      b6909a65
    • Christoffer Dall's avatar
      KVM: arm/arm64: vgic: Support level-triggered mapped interrupts · e40cc57b
      Christoffer Dall authored
      Level-triggered mapped IRQs are special because we only observe rising
      edges as input to the VGIC, and we don't set the EOI flag and therefore
      are not told when the level goes down, so that we can re-queue a new
      interrupt when the level goes up.
      
      One way to solve this problem is to side-step the logic of the VGIC and
      special case the validation in the injection path, but it has the
      unfortunate drawback of having to peak into the physical GIC state
      whenever we want to know if the interrupt is pending on the virtual
      distributor.
      
      Instead, we can maintain the current semantics of a level triggered
      interrupt by sort of treating it as an edge-triggered interrupt,
      following from the fact that we only observe an asserting edge.  This
      requires us to be a bit careful when populating the LRs and when folding
      the state back in though:
      
       * We lower the line level when populating the LR, so that when
         subsequently observing an asserting edge, the VGIC will do the right
         thing.
      
       * If the guest never acked the interrupt while running (for example if
         it had masked interrupts at the CPU level while running), we have
         to preserve the pending state of the LR and move it back to the
         line_level field of the struct irq when folding LR state.
      
         If the guest never acked the interrupt while running, but changed the
         device state and lowered the line (again with interrupts masked) then
         we need to observe this change in the line_level.
      
         Both of the above situations are solved by sampling the physical line
         and set the line level when folding the LR back.
      
       * Finally, if the guest never acked the interrupt while running and
         sampling the line reveals that the device state has changed and the
         line has been lowered, we must clear the physical active state, since
         we will otherwise never be told when the interrupt becomes asserted
         again.
      
      This has the added benefit of making the timer optimization patches
      (https://lists.cs.columbia.edu/pipermail/kvmarm/2017-July/026343.html) a
      bit simpler, because the timer code doesn't have to clear the active
      state on the sync anymore.  It also potentially improves the performance
      of the timer implementation because the GIC knows the state or the LR
      and only needs to clear the
      active state when the pending bit in the LR is still set, where the
      timer has to always clear it when returning from running the guest with
      an injected timer interrupt.
      Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Reviewed-by: default avatarEric Auger <eric.auger@redhat.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      e40cc57b
    • Christoffer Dall's avatar
      KVM: arm/arm64: Don't cache the timer IRQ level · 70450a9f
      Christoffer Dall authored
      The timer logic was designed after a strict idea of modeling an
      interrupt line level in software, meaning that only transitions in the
      level need to be reported to the VGIC.  This works well for the timer,
      because the arch timer code is in complete control of the device and can
      track the transitions of the line.
      
      However, as we are about to support using the HW bit in the VGIC not
      just for the timer, but also for VFIO which cannot track transitions of
      the interrupt line, we have to decide on an interface between the GIC
      and other subsystems for level triggered mapped interrupts, which both
      the timer and VFIO can use.
      
      VFIO only sees an asserting transition of the physical interrupt line,
      and tells the VGIC when that happens.  That means that part of the
      interrupt flow is offloaded to the hardware.
      
      To use the same interface for VFIO devices and the timer, we therefore
      have to change the timer (we cannot change VFIO because it doesn't know
      the details of the device it is assigning to a VM).
      
      Luckily, changing the timer is simple, we just need to stop 'caching'
      the line level, but instead let the VGIC know the state of the timer
      every time there is a potential change in the line level, and when the
      line level should be asserted from the timer ISR.  The VGIC can ignore
      extra notifications using its validate mechanism.
      Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Reviewed-by: default avatarJulien Thierry <julien.thierry@arm.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      70450a9f
    • Christoffer Dall's avatar
      KVM: arm/arm64: Factor out functionality to get vgic mmio requester_vcpu · 6c1b7521
      Christoffer Dall authored
      We are about to distinguish between userspace accesses and mmio traps
      for a number of the mmio handlers.  When the requester vcpu is NULL, it
      means we are handling a userspace access.
      
      Factor out the functionality to get the request vcpu into its own
      function, mostly so we have a common place to document the semantics of
      the return value.
      
      Also take the chance to move the functionality outside of holding a
      spinlock and instead explicitly disable and enable preemption.  This
      supports PREEMPT_RT kernels as well.
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      6c1b7521
    • Christoffer Dall's avatar
      KVM: arm/arm64: Remove redundant preemptible checks · 5a245750
      Christoffer Dall authored
      The __this_cpu_read() and __this_cpu_write() functions already implement
      checks for the required preemption levels when using
      CONFIG_DEBUG_PREEMPT which gives you nice error messages and such.
      Therefore there is no need to explicitly check this using a BUG_ON() in
      the code (which we don't do for other uses of per cpu variables either).
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      5a245750
    • Vasyl Gomonovych's avatar
      KVM: arm: Use PTR_ERR_OR_ZERO() · 4404b336
      Vasyl Gomonovych authored
      Fix ptr_ret.cocci warnings:
      virt/kvm/arm/vgic/vgic-its.c:971:1-3: WARNING: PTR_ERR_OR_ZERO can be used
      
      Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
      
      Generated by: scripts/coccinelle/api/ptr_ret.cocci
      Signed-off-by: default avatarVasyl Gomonovych <gomonovych@gmail.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      4404b336
    • Andrew Jones's avatar
      arm64: KVM: Hide PMU from guests when disabled · 0c0543a1
      Andrew Jones authored
      Since commit 93390c0a ("arm64: KVM: Hide unsupported AArch64 CPU
      features from guests") we can hide cpu features from guests. Apply
      this to a long standing issue where guests see a PMU available, but
      it's not, because it was not enabled by KVM's userspace.
      Signed-off-by: default avatarAndrew Jones <drjones@redhat.com>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      0c0543a1
  7. 11 Dec, 2017 1 commit
  8. 10 Dec, 2017 9 commits
    • Jeff Layton's avatar
      hpfs: don't bother with the i_version counter or f_version · 98087c05
      Jeff Layton authored
      HPFS does not set SB_I_VERSION and does not use the i_version counter
      internally.
      Signed-off-by: default avatarJeff Layton <jlayton@redhat.com>
      Signed-off-by: default avatarMikulas Patocka <mikulas@twibright.com>
      Reviewed-by: default avatarMikulas Patocka <mikulas@twibright.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      98087c05
    • Jiri Slaby's avatar
      futex: futex_wake_op, fix sign_extend32 sign bits · d70ef228
      Jiri Slaby authored
      sign_extend32 counts the sign bit parameter from 0, not from 1.  So we
      have to use "11" for 12th bit, not "12".
      
      This mistake means we have not allowed negative op and cmp args since
      commit 30d6e0a4 ("futex: Remove duplicated code and fix undefined
      behaviour") till now.
      
      Fixes: 30d6e0a4 ("futex: Remove duplicated code and fix undefined behaviour")
      Signed-off-by: default avatarJiri Slaby <jslaby@suse.cz>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Darren Hart <dvhart@infradead.org>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      d70ef228
    • Linus Torvalds's avatar
      Merge tag 'for-4.15-rc3-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux · 51090c5d
      Linus Torvalds authored
      Pull btrfs fixes from David Sterba:
       "This contains a few fixes (error handling, quota leak, FUA vs
        nobarrier mount option).
      
        There's one one worth mentioning separately - an off-by-one fix that
        leads to overwriting first byte of an adjacent page with 0, out of
        bounds of the memory allocated by an ioctl. This is under a privileged
        part of the ioctl, can be triggerd in some subvolume layouts"
      
      * tag 'for-4.15-rc3-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux:
        btrfs: Fix possible off-by-one in btrfs_search_path_in_tree
        Btrfs: disable FUA if mounted with nobarrier
        btrfs: fix missing error return in btrfs_drop_snapshot
        btrfs: handle errors while updating refcounts in update_ref_for_cow
        btrfs: Fix quota reservation leak on preallocated files
      51090c5d
    • Linus Torvalds's avatar
      Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc · 9c02e060
      Linus Torvalds authored
      Pull ARM SoC fixes from Olof Johansson:
      
       - A revert of all SCPI changes from the 4.15 merge window. They had
         regressions on the Amlogic platforms, and the submaintainer isn't
         around to fix these bugs due to vacation, etc. So we agreed to revert
         and revisit in next release cycle.
      
       - A series fixing a number of bugs for ARM CCN interconnect, around
         module unload, smp_processor_id() in preemptable context, and fixing
         some memory allocation failure checks.
      
       - A handful of devicetree fixes for different platforms, fixing
         warnings and errors that were previously ignored by the compiler.
      
       - The usual set of mostly minor fixes for different platforms.
      
      * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits)
        ARM64: dts: meson-gx: fix UART pclk clock name
        ARM: omap2: hide omap3_save_secure_ram on non-OMAP3 builds
        arm: dts: nspire: Add missing #phy-cells to usb-nop-xceiv
        ARM: dts: Fix dm814x missing phy-cells property
        ARM: dts: Fix elm interrupt compiler warning
        bus: arm-ccn: fix module unloading Error: Removing state 147 which has instances left.
        bus: arm-cci: Fix use of smp_processor_id() in preemptible context
        bus: arm-ccn: Fix use of smp_processor_id() in preemptible context
        bus: arm-ccn: Simplify code
        bus: arm-ccn: Check memory allocation failure
        bus: arm-ccn: constify attribute_group structures.
        firmware: arm_scpi: Revert updates made during v4.15 merge window
        arm: dts: marvell: Add missing #phy-cells to usb-nop-xceiv
        arm64: dts: sort vendor subdirectories in Makefile alphabetically
        meson-gx-socinfo: Fix package id parsing
        ARM: meson: fix spelling mistake: "Couln't" -> "Couldn't"
        ARM: dts: meson: fix the memory region of the GPIO interrupt controller
        ARM: dts: meson: correct the sort order for the the gpio_intc node
        MAINTAINERS: exclude other Socionext SoC DT files from ARM/UNIPHIER entry
        arm64: dts: uniphier: remove unnecessary interrupt-parent
        ...
      9c02e060
    • Linus Torvalds's avatar
      Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm · c465fc11
      Linus Torvalds authored
      Pull KVM fixes from Radim Krčmář:
       "ARM:
         - A number of issues in the vgic discovered using SMATCH
         - A bit one-off calculation in out stage base address mask (32-bit
           and 64-bit)
         - Fixes to single-step debugging instructions that trap for other
           reasons such as MMMIO aborts
         - Printing unavailable hyp mode as error
         - Potential spinlock deadlock in the vgic
         - Avoid calling vgic vcpu free more than once
         - Broken bit calculation for big endian systems
      
       s390:
         - SPDX tags
         - Fence storage key accesses from problem state
         - Make sure that irq_state.flags is not used in the future
      
        x86:
         - Intercept port 0x80 accesses to prevent host instability (CVE)
         - Use userspace FPU context for guest FPU (mainly an optimization
           that fixes a double use of kernel FPU)
         - Do not leak one page per module load
         - Flush APIC page address cache from MMU invalidation notifiers"
      
      * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (28 commits)
        KVM: x86: fix APIC page invalidation
        KVM: s390: Fix skey emulation permission check
        KVM: s390: mark irq_state.flags as non-usable
        KVM: s390: Remove redundant license text
        KVM: s390: add SPDX identifiers to the remaining files
        KVM: VMX: fix page leak in hardware_setup()
        KVM: VMX: remove I/O port 0x80 bypass on Intel hosts
        x86,kvm: remove KVM emulator get_fpu / put_fpu
        x86,kvm: move qemu/guest FPU switching out to vcpu_run
        KVM: arm/arm64: Fix broken GICH_ELRSR big endian conversion
        KVM: arm/arm64: kvm_arch_destroy_vm cleanups
        KVM: arm/arm64: Fix spinlock acquisition in vgic_set_owner
        kvm: arm: don't treat unavailable HYP mode as an error
        KVM: arm/arm64: Avoid attempting to load timer vgic state without a vgic
        kvm: arm64: handle single-step of hyp emulated mmio instructions
        kvm: arm64: handle single-step during SError exceptions
        kvm: arm64: handle single-step of userspace mmio instructions
        kvm: arm64: handle single-stepping trapped instructions
        KVM: arm/arm64: debug: Introduce helper for single-step
        arm: KVM: Fix VTTBR_BADDR_MASK BUG_ON off-by-one
        ...
      c465fc11
    • Olof Johansson's avatar
      Merge branch 'fixes' into for-next · 8be0b988
      Olof Johansson authored
      * fixes:
        ARM64: dts: meson-gx: fix UART pclk clock name
        ARM: dts: Fix dm814x missing phy-cells property
        ARM: dts: Fix elm interrupt compiler warning
        bus: arm-ccn: fix module unloading Error: Removing state 147 which has instances left.
        bus: arm-cci: Fix use of smp_processor_id() in preemptible context
        bus: arm-ccn: Fix use of smp_processor_id() in preemptible context
        bus: arm-ccn: Simplify code
        bus: arm-ccn: Check memory allocation failure
        bus: arm-ccn: constify attribute_group structures.
        meson-gx-socinfo: Fix package id parsing
        ARM: meson: fix spelling mistake: "Couln't" -> "Couldn't"
        ARM: dts: meson: fix the memory region of the GPIO interrupt controller
        ARM: dts: meson: correct the sort order for the the gpio_intc node
      8be0b988
    • Olof Johansson's avatar
      Merge tag 'amlogic-fixes-1' of... · ce39882e
      Olof Johansson authored
      Merge tag 'amlogic-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into fixes
      
      Amlogic fixes for v4.15-rc
      - GPIO interrupt fixes
      - socinfo fix for GX series
      - fix typo
      
      * tag 'amlogic-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
        ARM64: dts: meson-gx: fix UART pclk clock name
        meson-gx-socinfo: Fix package id parsing
        ARM: meson: fix spelling mistake: "Couln't" -> "Couldn't"
        ARM: dts: meson: fix the memory region of the GPIO interrupt controller
        ARM: dts: meson: correct the sort order for the the gpio_intc node
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      ce39882e
    • Olof Johansson's avatar
      Merge tag 'ccn/fixes-for-4.15' of git://git.linaro.org/people/pawel.moll/linux into fixes · 3dda7f63
      Olof Johansson authored
      bus: ARM CCN and CCI PMU driver fixes
      
      This is a bunch of fixes CCN and (guest starring this time) CCI drivers.
      
      * Check for potential of failed allocation for the driver name string
      * Manage CPU ID properly at allocation (both CCN and CCI)
      * Fix module unload warnings related to objects release order
      * Small improvements like using allocating printfs and proper
        attributes constification
      
      The one fixing potential issues have been cc-ed to stable.
      
      * tag 'ccn/fixes-for-4.15' of git://git.linaro.org/people/pawel.moll/linux:
        bus: arm-ccn: fix module unloading Error: Removing state 147 which has instances left.
        bus: arm-cci: Fix use of smp_processor_id() in preemptible context
        bus: arm-ccn: Fix use of smp_processor_id() in preemptible context
        bus: arm-ccn: Simplify code
        bus: arm-ccn: Check memory allocation failure
        bus: arm-ccn: constify attribute_group structures.
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      3dda7f63
    • Olof Johansson's avatar
      Merge tag 'omap-for-v4.15/fixes-dt-warnings' of... · 69b8df5d
      Olof Johansson authored
      Merge tag 'omap-for-v4.15/fixes-dt-warnings' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
      
      Two fixes for dts compiler warnings
      
      These recently started showing up with better dtc checks being
      introduced.
      
      * tag 'omap-for-v4.15/fixes-dt-warnings' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
        ARM: dts: Fix dm814x missing phy-cells property
        ARM: dts: Fix elm interrupt compiler warning
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      69b8df5d
  9. 09 Dec, 2017 1 commit
  10. 08 Dec, 2017 1 commit