- 01 Feb, 2021 5 commits
-
-
Geert Uytterhoeven authored
The Intel Lightning Mountain (LGM) DMA controller is only present on Intel Lightning Mountain SoCs. Hence add a dependency on X86, to prevent asking the user about this driver when configuring a kernel without Intel Lightning Mountain platform support. While at it, fix a misspelling of "Intel". Fixes: 32d31c79 ("dmaengine: Add Intel LGM SoC DMA support.") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210129131702.2656060-1-geert+renesas@glider.beSigned-off-by:
Vinod Koul <vkoul@kernel.org>
-
Geert Uytterhoeven authored
The DMACs (both SYS-DMAC and RT-DMAC) on R-Car V3U differ slightly from the DMACs on R-Car Gen2 and other R-Car Gen3 SoCs: 1. The per-channel registers are located in a second register block. Add support for mapping the second block, using the appropriate offsets and stride. 2. The common Channel Clear Register (DMACHCLR) was replaced by a per-channel register. Update rcar_dmac_chan_clear{,_all}() to handle this. As rcar_dmac_init() needs to clear the status before the individual channels are probed, channel index and base address initialization are moved forward. Inspired by a patch in the BSP by Phong Hoang <phong.hoang.wz@renesas.com>. Signed-off-by:Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by:
-
Geert Uytterhoeven authored
Extract the code to clear the status of one or all channels into their own helpers, to prepare for the different handling of the R-Car V3U SoC. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
-
Geert Uytterhoeven authored
Add a helper macro for iterating over all DMAC channels, taking into account the channel mask. Use it where appropriate, to simplify code. Restore "reverse Christmas tree" order of local variables while adding a new variable. Signed-off-by:
-
Geert Uytterhoeven authored
Document the compatible value for the Direct Memory Access Controller blocks in the Renesas R-Car V3U (R8A779A0) SoC. The most visible difference with DMAC blocks on other R-Car SoCs is the move of the per-channel registers to a separate register block. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
-
- 27 Jan, 2021 2 commits
-
-
Bjorn Helgaas authored
Fix misspelling of "physical". Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20210126205906.2918099-1-helgaas@kernel.orgSigned-off-by:
-
Thara Gopinath authored
When bam dma is "controlled remotely", thus far clocks were not controlled from the Linux. In this scenario, Linux was disabling runtime pm in bam dma driver and not doing any clock management in suspend/resume hooks. With introduction of crypto engine bam dma, the clock is a rpmh resource that can be controlled from both Linux and TZ/remote side. Now bam dma clock is getting enabled during probe even though the bam dma can be "controlled remotely". But due to clocks not being handled properly, bam_suspend generates a unbalanced clk_unprepare warning during system suspend. To fix the above issue and to enable proper clock-management, this patch enables runtim-pm and handles bam dma clocks in suspend/resume hooks if the clock node is present irrespective of controlled_remotely property. Signed-off-by:
Thara Gopinath <thara.gopinath@linaro.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by:
John Stultz <john.stultz@linaro.org> Reviewed-by:
Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210126211859.790892-1-thara.gopinath@linaro.orgSigned-off-by:
-
- 26 Jan, 2021 14 commits
-
-
Dave Jiang authored
Add a module parameter that overrides the SVA feature enabling. This keeps the driver in legacy mode even when intel_iommu=sm_on is set. In this mode, the descriptor fields must be programmed with dma_addr_t from the Linux DMA API for source, destination, and completion descriptors. Signed-off-by:
Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/161134110457.4005461.13171197785259115852.stgit@djiang5-desk3.ch.intel.comSigned-off-by:
-
Lubomir Rintel authored
There is no reason the Marvell MMP two-channel audio DMA driver would have to be built-in. Signed-off-by:
Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20210121110356.1768635-4-lkundrak@v3.skSigned-off-by:
-
Lubomir Rintel authored
There is no reason the Marvell MMP peripheral DMA driver would have to be built-in. Signed-off-by:
-
Lubomir Rintel authored
It's not used anywhere -- drop it. Signed-off-by:
-
Arnd Bergmann authored
The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210120131859.2056308-4-arnd@kernel.orgSigned-off-by:
-
Arnd Bergmann authored
The zte zx platform is getting removed, so this driver is no longer needed. Signed-off-by:
-
Arnd Bergmann authored
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Signed-off-by:
Barry Song <baohua@kernel.org> Cc: Barry Song <baohua@kernel.org> Link: https://lore.kernel.org/r/20210120131859.2056308-2-arnd@kernel.orgSigned-off-by:
-
Bjorn Andersson authored
The $ref for "intel,dma-poll-cnt" is missing an '/', causing dt_binding_check to fail. Fix this. Fixes: afd4df85 ("dt-bindings: dma: Add bindings for Intel LGM SoC") Signed-off-by:
-
Vinod Koul authored
[1] mentions the IOAT entry contains dmaengine subsystem file. So update the entry and remove the dmaengine files 1: https://lwn.net/Articles/842415/ Link: https://lore.kernel.org/r/20210117070229.2537866-1-vkoul@kernel.orgSigned-off-by:
-
Vinod Koul authored
Somehow dmaengine header files are missed in the entry so update it Link: https://lore.kernel.org/r/20210117070804.2539698-1-vkoul@kernel.orgSigned-off-by:
-
Paul Cercueil authored
Add support for the JZ4760 and JZ4760B SoCs. Both SoCs have only 5 DMA channels per chip. The JZ4760B introduced the DCKES/DCKEC registers. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210120105322.16116-2-paul@crapouillou.netSigned-off-by:
-
Paul Cercueil authored
Add ingenic,jz4760-dma and ingenic,jz4760b-dma compatible strings to support the DMA engines present in the JZ4760 and JZ4760B SoCs. Signed-off-by:
-
Fabio Estevam authored
Use of_device_get_match_data() to make the code simpler. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210118121549.1625217-2-festevam@gmail.comSigned-off-by:
-
Fabio Estevam authored
Since 5.10-rc1, i.MX has been converted to a devicetree-only platform. The platform data support in this driver was only used for non-DT platforms. Remove the platform data support as it has no more users. Signed-off-by:
-
- 17 Jan, 2021 2 commits
-
-
Dave Jiang authored
Add DMA_PRIVATE attribute flag to idxd DMA channels. The dedicated WQs are expected to be used by a single client and not shared. While doing NTB testing this mistake was discovered, which prevented ntb_transport from requesting DSA wqs as DMA channels via dma_request_channel(). Reported-by:
Srinijia Kambham <srinija.kambham@intel.com> Signed-off-by:
-
Xu Wang authored
fix semicolon.cocci warning: drivers/dma/qcom/gpi.c:1703:2-3: Unneeded semicolon Signed-off-by:
Xu Wang <vulab@iscas.ac.cn> Link: https://lore.kernel.org/r/20210115100040.33364-1-vulab@iscas.ac.cnSigned-off-by:
-
- 13 Jan, 2021 6 commits
-
-
Ferry Toth authored
On Intel Tangier B0 and Anniedale the interrupt line, disregarding to have different numbers, is shared between HSU DMA and UART IPs. Thus on such SoCs we are expecting that IRQ handler is called in UART driver only. hsu_pci_irq was handling the spurious interrupt from HSU DMA by returning immediately. This wastes CPU time and since HSU DMA and HSU UART interrupt occur simultaneously they race to be handled causing delay to the HSU UART interrupt handling. Fix this by disabling the interrupt entirely. Fixes: 4831e0d9 ("serial: 8250_mid: handle interrupt correctly in DMA case") Signed-off-by:
Ferry Toth <ftoth@exalondelft.nl> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20210112223749.97036-1-ftoth@exalondelft.nlSigned-off-by:
-
Peter Ujfalusi authored
The ret does not need to be initialized to 0 in the tisci channel config functions. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20210113114923.9231-4-peter.ujfalusi@gmail.comSigned-off-by:
-
Peter Ujfalusi authored
The UDMA and BCDMA can provide higher throughput if the burst_size of the channel is changed from it's default (which is 64 bytes) for Ultra-high and high capacity channels. This performance benefit is even more visible when the buffers are aligned with the burst_size configuration. The am654 does not have a way to change the burst size, but it is using 64 bytes burst, so increasing the copy_align from 8 bytes to 64 (and clients taking that into account) can increase the throughput as well. Numbers gathered on j721e: echo 8000000 > /sys/module/dmatest/parameters/test_buf_size echo 2000 > /sys/module/dmatest/parameters/timeout echo 50 > /sys/module/dmatest/parameters/iterations echo 1 > /sys/module/dmatest/parameters/max_channels Prior this patch: ~1.3 GB/s After this patch: ~1.8 GB/s with 1 byte alignment: ~1.7 GB/s Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210113114923.9231-3-peter.ujfalusi@gmail.comSigned-off-by:
-
Peter Ujfalusi authored
Some DMA device can benefit with higher order of alignment than the maximum of 64 bytes currently defined. Define 128 and 256 bytes alignment for these devices. Signed-off-by:
-
Vignesh Raghavendra authored
BCDMA RX channels have one flow per channel, therefore set the rflow_cnt to rchan_cnt. Without this patch, request for BCDMA RX channel allocation fails as rflow_cnt is 0 thus fails to reserve a rflow for the channel. Fixes: 88448980 ("dmaengine: ti: k3-udma: Add support for BCDMA channel TPL handling") Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Acked-by:
-
Nathan Chancellor authored
When building with CONFIG_UBSAN_UNSIGNED_OVERFLOW, clang decides not to inline gpi_update_reg, which causes a linkage failure around __bad_mask: ld.lld: error: undefined symbol: __bad_mask >>> referenced by bitfield.h:119 (include/linux/bitfield.h:119) >>> dma/qcom/gpi.o:(gpi_update_reg) in archive drivers/built-in.a >>> referenced by bitfield.h:119 (include/linux/bitfield.h:119) >>> dma/qcom/gpi.o:(gpi_update_reg) in archive drivers/built-in.a If gpi_update_reg is not inlined, the mask value will not be known at compile time so the check in field_multiplier stays in the final object file, causing the above linkage failure. Always inline gpi_update_reg so that this check can never fail. Fixes: 5d0c3533 ("dmaengine: qcom: Add GPI dma driver") Link: https://github.com/ClangBuiltLinux/linux/issues/1243Signed-off-by:
Nathan Chancellor <natechancellor@gmail.com> Link: https://lore.kernel.org/r/20210112191214.1264793-1-natechancellor@gmail.comSigned-off-by:
-
- 12 Jan, 2021 5 commits
-
-
Christophe JAILLET authored
A 'dma_pool_destroy()' call is missing in the remove function. Add it. This call is already made in the error handling path of the probe function. Fixes: 47e20577 ("dmaengine: Add Actions Semi Owl family S900 DMA driver") Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/20201212162535.95727-1-christophe.jaillet@wanadoo.frSigned-off-by:
-
Christophe JAILLET authored
In case of error, the previous 'fsl_dma_chan_probe()' calls must be undone by some 'fsl_dma_chan_remove()', as already done in the remove function. It was added in the remove function in commit 77cd62e8 ("fsldma: allow Freescale Elo DMA driver to be compiled as a module") Fixes: d3f620b2 ("fsldma: simplify IRQ probing and handling") Signed-off-by:
-
Christophe JAILLET authored
A 'irq_dispose_mapping()' call is missing in the remove function. Add it. This is needed to undo the 'irq_of_parse_and_map() call from the probe function and already part of the error handling path of the probe function. It was added in the probe function only in commit d3f620b2 ("fsldma: simplify IRQ probing and handling") Fixes: 77cd62e8 ("fsldma: allow Freescale Elo DMA driver to be compiled as a module") Signed-off-by:
-
Amireddy Mallikarjuna reddy authored
Add DMA controller driver for Lightning Mountain (LGM) family of SoCs. The main function of the DMA controller is the transfer of data from/to any peripheral to/from the memory. A memory to memory copy capability can also be configured. This ldma driver is used for configure the device and channnels for data and control paths. Signed-off-by:
Amireddy Mallikarjuna reddy <mallikarjunax.reddy@linux.intel.com> Link: https://lore.kernel.org/r/5fc54eb7ccfad4f8dd812b66b884054fc55cf050.1606905330.git.mallikarjunax.reddy@linux.intel.comSigned-off-by:
-
Amireddy Mallikarjuna reddy authored
Add DT bindings YAML schema for DMA controller driver of Lightning Mountain (LGM) SoC. Signed-off-by:
-
- 08 Jan, 2021 4 commits
-
-
Zheng Yongjun authored
mutex lock can be initialized automatically with DEFINE_MUTEX() rather than explicitly calling mutex_init(). Signed-off-by:
Zheng Yongjun <zhengyongjun3@huawei.com> Acked-by:
-
Alexandre Belloni authored
linux/platform_data/dma-atmel.h is only used by the at_hdmac driver. Move the CFG bits definitions back in at_hdmac_regs.h and the remaining definitions in the driver. Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20201228203022.2674133-1-alexandre.belloni@bootlin.comSigned-off-by:
-
Cristian Ciocaltea authored
The DMA controller present on the Actions Semi S500 SoC is compatible with the S900 variant, so add it to the list of devices supported by the Actions Semi Owl DMA driver. Additionally, order the entries alphabetically. Signed-off-by:
Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/88dc9dc064fd4c71f7ad46f172b05b09b9777e42.1609263738.git.cristian.ciocaltea@gmail.comSigned-off-by:
-
Cristian Ciocaltea authored
Add a new compatible string corresponding to the DMA controller found in the S500 variant of the Actions Semi Owl SoCs family. Additionally, order the entries alphabetically. Signed-off-by:
-
- 27 Dec, 2020 2 commits
-
-
Linus Torvalds authored
-
Linus Torvalds authored
Since commit 36e2c742 ("fs: don't allow splice read/write without explicit ops") we've required that file operation structures explicitly enable splice support, rather than falling back to the default handlers. Most /proc files use the indirect 'struct proc_ops' to describe their file operations, and were fixed up to support splice earlier in commits 40be821d..b24c30c6, but the mountinfo files interact with the VFS directly using their own 'struct file_operations' and got missed as a result. This adds the necessary support for splice to work for /proc/*/mountinfo and friends. Reported-by:
Joan Bruguera Micó <joanbrugueram@gmail.com> Reported-by:
Jussi Kivilinna <jussi.kivilinna@iki.fi> Link: https://bugzilla.kernel.org/show_bug.cgi?id=209971 Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Christoph Hellwig <hch@lst.de> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
-
