- 05 May, 2022 21 commits
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 164 bytes. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/c98e577996a71ae96145ee6da94aa18fd9ea85b9.1649865241.git.geert+renesas@glider.be
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 140 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 246 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 40 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 168 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 164 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 148 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 148 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 152 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 232 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 201 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 784 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 349 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 445 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 197 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 142 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 114 bytes. Signed-off-by:
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Geert Uytterhoeven authored
Replace the full descriptions of reserved register fields by shorthands with a negative field width, and merge adjacent reserved fields. This reduces kernel size by 769 bytes. Signed-off-by:
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Geert Uytterhoeven authored
The PULMD bits and the SEC bit in the PORTCR register descriptions on SH/R-Mobile SoCs are either unused or unsupported. Describe them as reserved bits using a negative field width value, and drop the corresponding dummy enum IDs. This reduces kernel size by 2832 (R-Mobile APE6), 2544 (R-Mobile A1), and/or 3228 (SH-Mobile AG5) bytes. Signed-off-by:
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Geert Uytterhoeven authored
Currently, reserved register fields must be fully described using dummy enum IDs (zeroes), one for each possible state (2^bits states). Add support for describing reserved fields using negative field width values as shorthands, thus removing the need for dummy values. Apart from the obvious size reduction due to the removal of the dummy values, this will also enable merging adjacent reserved fields into a single field, reducing the number of fields to describe, and thus kernel size. Update the checker accordingly. Signed-off-by:
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Geert Uytterhoeven authored
All fields in the IPSR registers on RZ/G1C have the same width, but the driver describes them using the PINMUX_CFG_REG_VAR() macro, which is intended for fields with different widths. Convert the description to use the PINMUX_CFG_REG() macro for fixed-width fields instead. This reduces kernel size by 162 bytes. Signed-off-by:
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- 03 May, 2022 4 commits
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Yang Yingliang authored
It will cause null-ptr-deref when using 'res', if platform_get_resource() returns NULL, so move using 'res' after devm_ioremap_resource() that will check it to avoid null-ptr-deref. And use devm_platform_get_and_ioremap_resource() to simplify code. Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220429082637.1308182-2-yangyingliang@huawei.comSigned-off-by:
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Yang Yingliang authored
It will cause null-ptr-deref when using 'res', if platform_get_resource() returns NULL, so move using 'res' after devm_ioremap_resource() that will check it to avoid null-ptr-deref. And use devm_platform_get_and_ioremap_resource() to simplify code. Fixes: c7977ec4 ("pinctrl: sh-pfc: Convert to platform_get_*()") Signed-off-by:
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Geert Uytterhoeven authored
Unlike on R-Car Gen3 SoCs, setting a bit to zero in a GPIO / Peripheral Function Select Register (GPSRn) on R-Car S4-8 is not always sufficient to configure a pin for GPIO. For I2C-capable pins, the I2C function must also be explicitly disabled in the corresponding Module Select Register (MODSELn). Add the missing FN_SEL_I2Ci_0 function enums to the pinmux_data[] array by temporarily overriding the GP_1_j_FN function enum to expand to two enums: the original GP_1_j_FN enum to configure the GPSR register bits, and the missing FN_SEL_I2Ci_0 enum to configure the MODSEL register bits. Fixes: 030ac6d7 ("pinctrl: renesas: Initial R8A779F0 PFC support") Signed-off-by:
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Geert Uytterhoeven authored
Unlike on R-Car Gen3 SoCs, setting a bit to zero in a GPIO / Peripheral Function Select Register (GPSRn) on R-Car V3U is not always sufficient to configure a pin for GPIO. For I2C-capable pins, the I2C function must also be explicitly disabled in the corresponding Module Select Register (MODSELn). Add the missing FN_SEL_I2Ci_0 function enums to the pinmux_data[] array by temporarily overriding the GP_2_j_FN function enum to expand to two enums: the original GP_2_j_FN enum to configure the GSPR register bits, and the missing FN_SEL_I2Ci_0 enum to configure the MODSEL register bits. Fixes: 741a7370 ("pinctrl: renesas: Initial R8A779A0 (V3U) PFC support") Signed-off-by:
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- 20 Apr, 2022 9 commits
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Geert Uytterhoeven authored
The PIN_CFG_* capabilities are always listed in the order they are defined, except in the "TMS/SWDIO" pin definition. Fix the order, to increase uniformity. Signed-off-by:
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Geert Uytterhoeven authored
The last __init annotations were removed from these source files almost one decade ago. Signed-off-by:
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Lad Prabhakar authored
GPIO (PINCTRL) block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so instead of selecting PINCTRL_RZG2L config for each SoC select PINCTRL_RZG2L config option if ARCH_RZG2L is enabled. The ARCH_RZG2L config option is already selected by ARCH_R9A07G043, ARCH_R9A07G044 and ARCH_R9A07G054. Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220406075318.14385-1-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by:
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Biju Das authored
RZ/G2UL SoC has fewer pins compared to RZ/G2L and the port pin definitions are different compared to RZ/G2L. This patch adds a new compatible to take care of these differences by adding r9a07g043_data with r9a07g043_gpio_configs and rzg2l_dedicated_pins.common. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
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Geert Uytterhoeven authored
Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77995 PFC driver. They are to be used when a QSPI Flash, Octal-SPI Flash, or HyperFlash is connected. Signed-off-by:
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Geert Uytterhoeven authored
Add pins, groups, and functions for the SPI Multi I/O Bus Controller (RPC-IF) to the R8A77990 PFC driver. They are to be used when an Octal-SPI Flash or HyperFlash is connected. Redefine the QSPI[01] pin groups using the RPC DQ[0:7] pin data, to save memory. Signed-off-by:
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Wolfram Sang authored
According to R-Car Gen3 HW documentation 2.20 onwards, drive-strength is introduced to r8a77990. It is also documented for r8a774c0. Add it to the pinctrl driver. Signed-off-by:
LUU HOAI <hoai.luu.ub@renesas.com> Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220320092542.2308-3-wsa+renesas@sang-engineering.comSigned-off-by:
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Wolfram Sang authored
Needed to support R-Car E3 and RZ/G2E drive regs. Signed-off-by:
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Geert Uytterhoeven authored
The checker code to iterate over all drive strength and bias register description items is cumbersome, due to the repeated calculation of indices, and the use of hardcoded array sizes. The latter was done under the assumption they would never need to be changed, which turned out to be false. Increase readability by introducing helper macros to access drive strength and bias register description items. Increase maintainability by replacing hardcoded numbers by array sizes calculated at compile-time. Signed-off-by:
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- 19 Apr, 2022 2 commits
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Biju Das authored
Document Renesas RZ/G2UL pinctrl bindings. RZ/G2UL GPIO block is almost identical to RZ/G2L and has lesser pins compared to RZ/G2L. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220315152717.20045-1-biju.das.jz@bp.renesas.comSigned-off-by:
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Geert Uytterhoeven authored
"a * (1 << b)" == "a << b". Signed-off-by:
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- 03 Apr, 2022 4 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-traceLinus Torvalds authored
Pull more tracing updates from Steven Rostedt: - Rename the staging files to give them some meaning. Just stage1,stag2,etc, does not show what they are for - Check for NULL from allocation in bootconfig - Hold event mutex for dyn_event call in user events - Mark user events to broken (to work on the API) - Remove eBPF updates from user events - Remove user events from uapi header to keep it from being installed. - Move ftrace_graph_is_dead() into inline as it is called from hot paths and also convert it into a static branch. * tag 'trace-v5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace: tracing: Move user_events.h temporarily out of include/uapi ftrace: Make ftrace_graph_is_dead() a static branch tracing: Set user_events to BROKEN tracing/user_events: Remove eBPF interfaces tracing/user_events: Hold event_mutex during dyn_event_add proc: bootconfig: Add null pointer check tracing: Rename the staging files for trace_events
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds authored
Pull clk fix from Stephen Boyd: "A single revert to fix a boot regression seen when clk_put() started dropping rate range requests. It's best to keep various systems booting so we'll kick this out and try again next time" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: Revert "clk: Drop the rate range on clk_put()"
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 fixes from Thomas Gleixner: "A set of x86 fixes and updates: - Make the prctl() for enabling dynamic XSTATE components correct so it adds the newly requested feature to the permission bitmap instead of overwriting it. Add a selftest which validates that. - Unroll string MMIO for encrypted SEV guests as the hypervisor cannot emulate it. - Handle supervisor states correctly in the FPU/XSTATE code so it takes the feature set of the fpstate buffer into account. The feature sets can differ between host and guest buffers. Guest buffers do not contain supervisor states. So far this was not an issue, but with enabling PASID it needs to be handled in the buffer offset calculation and in the permission bitmaps. - Avoid a gazillion of repeated CPUID invocations in by caching the values early in the FPU/XSTATE code. - Enable CONFIG_WERROR in x86 defconfig. - Make the X86 defconfigs more useful by adapting them to Y2022 reality" * tag 'x86-urgent-2022-04-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/fpu/xstate: Consolidate size calculations x86/fpu/xstate: Handle supervisor states in XSTATE permissions x86/fpu/xsave: Handle compacted offsets correctly with supervisor states x86/fpu: Cache xfeature flags from CPUID x86/fpu/xsave: Initialize offset/size cache early x86/fpu: Remove unused supervisor only offsets x86/fpu: Remove redundant XCOMP_BV initialization x86/sev: Unroll string mmio with CC_ATTR_GUEST_UNROLL_STRING_IO x86/config: Make the x86 defconfigs a bit more usable x86/defconfig: Enable WERROR selftests/x86/amx: Update the ARCH_REQ_XCOMP_PERM test x86/fpu/xstate: Fix the ARCH_REQ_XCOMP_PERM implementation
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