- 03 Mar, 2023 13 commits
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Kuogee Hsieh authored
At sc7280, pingpong block is used to management the dither effects to reduce distortion at panel. Currently pingpong-0 base offset is wrongly set at 0x59000. This mistake will not cause system to crash. However it will make dither not work. This patch correct sc7280 ping pong-0 block base offset. Changes in v2: -- add more details info n regrading of pingpong block at commit text Fixes: 591e34a0 ("drm/msm/disp/dpu1: add support for display for SC7280 target") Signed-off-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/524332/ Link: https://lore.kernel.org/r/1677533800-3125-1-git-send-email-quic_khsieh@quicinc.comSigned-off-by:
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Dmitry Baryshkov authored
The rewritten dpu_hw_ctl_setup_blendstage() can lightly smash the stack when setting the SSPP_NONE pipe. However it was unnoticed until the kernel was tested under AOSP (with some kind of stack protection/check). This fixes the following backtrace: Unexpected kernel BRK exception at EL1 Internal error: BRK handler: 00000000f20003e8 [#1] PREEMPT SMP Hardware name: Thundercomm Dragonboard 845c (DT) pstate: a0400005 (NzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : dpu_hw_ctl_setup_blendstage+0x26c/0x278 [msm] lr : _dpu_crtc_blend_setup+0x4b4/0x5a0 [msm] sp : ffffffc00bdcb720 x29: ffffffc00bdcb720 x28: ffffff8085debac0 x27: 0000000000000002 x26: ffffffd74af18320 x25: ffffff8083af75a0 x24: ffffffc00bdcb878 x23: 0000000000000001 x22: 0000000000000000 x21: ffffff8085a70000 x20: ffffff8083012dc0 x19: 0000000000000001 x18: 0000000000000000 x17: 000000040044ffff x16: 045000f4b5593519 x15: 0000000000000000 x14: 000000000000000b x13: 0000000000000001 x12: 0000000000000000 x11: 0000000000000001 x10: ffffffc00bdcb764 x9 : ffffffd74af06a08 x8 : 0000000000000001 x7 : 0000000000000001 x6 : 0000000000000000 x5 : ffffffc00bdcb878 x4 : 0000000000000002 x3 : ffffffffffffffff x2 : ffffffc00bdcb878 x1 : 0000000000000000 x0 : 0000000000000002 Call trace: dpu_hw_ctl_setup_blendstage+0x26c/0x278 [msm] _dpu_crtc_blend_setup+0x4b4/0x5a0 [msm] dpu_crtc_atomic_begin+0xd8/0x22c [msm] drm_atomic_helper_commit_planes+0x80/0x208 [drm_kms_helper] msm_atomic_commit_tail+0x134/0x6f0 [msm] commit_tail+0xa4/0x1a4 [drm_kms_helper] drm_atomic_helper_commit+0x170/0x184 [drm_kms_helper] drm_atomic_commit+0xac/0xe8 drm_mode_atomic_ioctl+0xbf0/0xdac drm_ioctl_kernel+0xc4/0x178 drm_ioctl+0x2c8/0x608 __arm64_sys_ioctl+0xa8/0xec invoke_syscall+0x44/0x104 el0_svc_common.constprop.0+0x44/0xec do_el0_svc+0x38/0x98 el0_svc+0x2c/0xb4 el0t_64_sync_handler+0xb8/0xbc el0t_64_sync+0x1a0/0x1a4 Code: 52800016 52800017 52800018 17ffffc7 (d4207d00) Fixes: 4488f71f ("drm/msm/dpu: simplify blend configuration") Reported-by:
Amit Pundir <amit.pundir@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
DPU driver has been using the DPU_CLK_CTRL_CURSOR prefix for the DMA SSPP blocks used for the cursor planes. This has lead to the confusion at least for the MSM8998 platform. In preparation to supporting the cursor SSPP blocks, use proper enum values to index DMA SSPP clock controls. Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550 on top of next-20230116 Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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Dmitry Baryshkov authored
DMA2 and DMA3 planes on msm8998 should use corresponding DMA2 and DMA3 clocks rather than CURSOR0/1 clocks (which are used for the CURSOR planes). Correct corresponding SSPP declarations. Fixes: 94391a14 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Cc: Jami Kettunen <jami.kettunen@somainline.org> Reviewed-by:
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Dmitry Baryshkov authored
The msm8998 doesn't seem to support DIM_LAYER, so drop it from the supported features mask. Fixes: 2d8a4edb ("drm/msm/dpu: use feature bit for LM combined alpha check") Fixes: 94391a14 ("drm/msm/dpu1: Add MSM8998 to hw catalog") Signed-off-by:
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Dmitry Baryshkov authored
QSEED4 is a newer variant of QSEED3LITE, which should be used on sm6115. Fix the used feature masks. Signed-off-by:
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Dmitry Baryshkov authored
QSEED4 is a newer variant of QSEED3LITE, which should be used on sm8250 and sm8350. Fix the DPU caps structure and used feature masks. Fixes: d21fc5df ("drm/msm/dpu1: add support for qseed3lite used on sm8250") Fixes: 0e91bcbb ("drm/msm/dpu: Add SM8350 to hw catalog") Signed-off-by:
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Dmitry Baryshkov authored
QSEED4 is a newer variant of QSEED3LITE, which should be used on sm8450. Fix the used feature masks. Fixes: 100d7ef6 ("drm/msm/dpu: add support for SM8450") Signed-off-by:
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Dmitry Baryshkov authored
QSEED4 is a newer variant of QSEED3LITE, which should be used on sc8280xp. Fix the DPU caps structure and used feature masks. Fixes: 4a352c2f ("drm/msm/dpu: Introduce SC8280XP") Signed-off-by:
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Dmitry Baryshkov authored
QSEED4 is a newer variant of QSEED3LITE, which should be used on sm8550. Fix the DPU caps structure and used feature masks. Fixes: efcd0107 ("drm/msm/dpu: add support for SM8550") Signed-off-by:
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Dmitry Baryshkov authored
According to vendor DTS files both sm6115 and qcm2290 should have max_mixer_width set to 2048 (DEFAULT_DPU_LINE_WIDTH). Correct it. Fixes: 3581b706 ("drm/msm/disp/dpu1: add support for display on SM6115") Fixes: 5334087e ("drm/msm: add support for QCM2290 MDSS") Signed-off-by:
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Dmitry Baryshkov authored
Change sc7180's ctl block len to 0x1dc. Fixes: 7bdc0c4b ("msm:disp:dpu1: add support for display for SC7180 target") Signed-off-by:
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Dmitry Baryshkov authored
Fix typo in the name of the sblk structure for the sm8550's dma_sblk_5. Fixes: efcd0107 ("drm/msm/dpu: add support for SM8550") Signed-off-by:
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- 28 Feb, 2023 2 commits
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Dmitry Baryshkov authored
QCM2290 doesn't seem to support reg-dma, UBWC and CSC. Drop corresponding features being incorrectly enabled for qcm2290. Cc: Loic Poulain <loic.poulain@linaro.org> Fixes: 5334087e ("drm/msm: add support for QCM2290 MDSS") Reviewed-by:
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Dmitry Baryshkov authored
The SC8280XP also has a black hole at the top of MDP_TOP region. Set corresponding bit to disable access to that region. Fixes: 4a352c2f ("drm/msm/dpu: Introduce SC8280XP") Reviewed-by:
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- 22 Feb, 2023 9 commits
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Johan Hovold authored
A recent commit moved enabling of runtime PM from adreno_gpu_init() to adreno_load_gpu() (called on first open()), which means that unbind() may now be called with runtime PM disabled in case the device was never opened in between. Make sure to only forcibly suspend and disable runtime PM at unbind() in case runtime PM has been enabled to prevent a disable count imbalance. This specifically avoids leaving runtime PM disabled when the device is later opened after a successful bind: msm_dpu ae01000.display-controller: [drm:adreno_load_gpu [msm]] *ERROR* Couldn't power up the GPU: -13 Fixes: 4b18299b ("drm/msm/adreno: Defer enabling runpm until hw_init()") Reported-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/lkml/20230203181245.3523937-1-quic_bjorande@quicinc.com Cc: stable@vger.kernel.org # 6.0 Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/523549/ Link: https://lore.kernel.org/r/20230221101430.14546-2-johan+linaro@kernel.orgSigned-off-by:
Rob Clark <robdclark@chromium.org>
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Dmitry Baryshkov authored
The rptr_addr is set in the preempt_init_ring(), which is called from a5xx_gpu_init(). It uses shadowptr() to set the address, however the shadow_iova is not yet initialized at that time. Move the rptr_addr setting to the a5xx_preempt_hw_init() which is called after setting the shadow_iova, getting the correct value for the address. Fixes: 8907afb4 ("drm/msm: Allow a5xx to mark the RPTR shadow as privileged") Suggested-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
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Dmitry Baryshkov authored
Quoting Yassine: ring->memptrs->rptr is never updated and stays 0, so the comparison always evaluates to false and get_next_ring always returns ring 0 thinking it isn't empty. Fix this by calling get_rptr() instead of reading rptr directly. Reported-by:
Yassine Oudjana <y.oudjana@protonmail.com> Fixes: b1fc2839 ("drm/msm: Implement preemption for A5XX targets") Signed-off-by:
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Dmitry Baryshkov authored
A530 has highest bank bit equal to 15 (like A540). Fix values written to REG_A5XX_RB_MODE_CNTL and REG_A5XX_TPL1_MODE_CNTL registers. Fixes: 1d832ab3 ("drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs") Signed-off-by:
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Dmitry Baryshkov authored
Rather than writing CP_PREEMPT_ENABLE_GLOBAL twice, follow the vendor kernel and set CP_PREEMPT_ENABLE_LOCAL register instead. a5xx_submit() will override it during submission, but let's get the sequence correct. Fixes: b1fc2839 ("drm/msm: Implement preemption for A5XX targets") Signed-off-by:
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Douglas Anderson authored
If, for whatever reason, we're trying process adreno_runtime_resume() at the same time that a6xx_destroy() is running then things can go boom. Specifically adreno_runtime_resume() will eventually call a6xx_pm_resume() and that may try to resume the gmu. Let's grab the GMU lock as we're destroying the GMU. That will solve the race because a6xx_pm_resume() grabs the same lock. That makes the access of `gmu->initialized` in a6xx_gmu_resume() safe. We'll also return an error code in a6xx_gmu_resume() if we see that `gmu->initialized` was false. If this happens we'll bail out of the rest of a6xx_pm_resume(), which is good because the rest of that function is also not good to do if we're racing with a6xx_destroy(). Signed-off-by:
Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/521232/ Link: https://lore.kernel.org/r/20230202104822.1.I0e49003bf4dd1dead9be4a29dbee41f3b1236e48@changeidSigned-off-by:
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Thomas Zimmermann authored
Do not run drm_fb_helper_unprepare() if fbdev allocation fails. Avoids access to an uninitialized pointer. Original bug report is at [1]. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Fixes: 3fb1f62f ("drm/fb-helper: Remove drm_fb_helper_unprepare() from drm_fb_helper_fini()") Link: https://lore.kernel.org/oe-kbuild-all/202302220810.9dymwCQ8-lkp@intel.com/ # 1 Reviewed-by:
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Rob Clark authored
The error path cleanup expects that chain and syncobj are either NULL or valid pointers. But post_deps was not allocated with __GFP_ZERO. Fixes: ab723b7a ("drm/msm: Add syncobj support.") Signed-off-by:
Dmitry Osipenko <dmitry.osipenko@collabora.com> Patchwork: https://patchwork.freedesktop.org/patch/523051/ Link: https://lore.kernel.org/r/20230215235048.1166484-1-robdclark@gmail.com
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Rob Clark authored
Back-merge of previous cycles msm-fixes for kexec fix (to avoid merge conflict) Signed-off-by:
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- 30 Jan, 2023 1 commit
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Rob Clark authored
The existing no-op shims for when PM_DEVFREQ (or an individual governor) only do half the job. The governor specific config/tuning structs need to be available to avoid compile errors in drivers using devfreq. Fixes: 6563f60f ("drm/msm/gpu: Add devfreq tuning debugfs") Signed-off-by:
MyungJoo Ham <myungjoo.ham@samsung.com> Acked-by:
Chanwoo Choi <cw00.choi@samsung.com> Patchwork: https://patchwork.freedesktop.org/patch/519801/ Link: https://lore.kernel.org/r/20230123153745.3185032-1-robdclark@gmail.com
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- 26 Jan, 2023 9 commits
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Dmitry Baryshkov authored
The function dpu_plane_sspp_atomic_update() updates pdpu->is_rt_pipe flag, but after the commit 854f6f1c ("drm/msm/dpu: update the qos remap only if the client type changes") it sets the flag late, after all the qos functions have updated QoS programming. Move the flag update back to the place where it happened before the mentioned commit to let the pipe be programmed according to its current RT/non-RT state. Fixes: 854f6f1c ("drm/msm/dpu: update the qos remap only if the client type changes") Signed-off-by:
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Dmitry Baryshkov authored
According to downstream (bengal-sde.dtsi), the sm6115 uses UBWC 1.0. Change the catalog entry accordingly. Signed-off-by:
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Dmitry Baryshkov authored
Extend dpu_hw_sspp_setup_format() to also handle the UBWC 1.0 case. Signed-off-by:
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Dmitry Baryshkov authored
On MSM8960 the HDMI PHY provides the PLL clock to the MMCC. As we are preparing to convert the MSM8960 to use DT clocks properties (rather than global clock names), register the OF clock provider. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/519211/ Link: https://lore.kernel.org/r/20230119132219.2479775-5-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
Replace parent_names usage with parent_data. Note, that this makes the PLL default to board's `pxo_board' clock rather than just `pxo' clock, as we are on a way to deprecate the global cxo/pxo clocks. Signed-off-by:
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Dmitry Baryshkov authored
Eventually all HDMI PHYs are going to provide the HDMI PLL clock to the MMCC. Add #clock-cells property required to provide the HDMI PLL clock to other devices. Signed-off-by:
Rob Herring <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/519213/ Link: https://lore.kernel.org/r/20230119132219.2479775-3-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
Add pxo clock to the 8960 bindings (used by the HDMI PLL) Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/519206/ Link: https://lore.kernel.org/r/20230119132219.2479775-2-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
It was left unnoticed during the review that even if there is no OPP table in device tree, one will be created by a call to the function devm_pm_opp_set_clkname(). This leads to dsi_mgr_bridge_mode_valid() rejecting all modes if DT contains no OPP table for the DSI host. Rework dsi_mgr_bridge_mode_valid() to handle this case by actually checking that the table is populated with frequency entries before returning an error. Fixes: 8328041b ("drm/msm/dsi: implement opp table based check for dsi_mgr_bridge_mode_valid()") Signed-off-by:
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Marijn Suijten authored
Add missing DSC hardware block register ranges to the snapshot utility to include them in dmesg (on MSM_DISP_SNAPSHOT_DUMP_IN_CONSOLE) and the kms debugfs file. Signed-off-by:
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- 24 Jan, 2023 6 commits
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Jiasheng Jiang authored
As kzalloc may fail and return NULL pointer, it should be better to check the return value in order to avoid the NULL pointer dereference. Fixes: 1cff7440 ("drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset.") Signed-off-by:
Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by:
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Jiasheng Jiang authored
As kzalloc may fail and return NULL pointer, it should be better to check pstates in order to avoid the NULL pointer dereference. Fixes: 25fdd593 ("drm/msm: Add SDM845 DPU support") Signed-off-by:
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Jiasheng Jiang authored
As kzalloc may fail and return NULL pointer, it should be better to check cstate in order to avoid the NULL pointer dereference in __drm_atomic_helper_crtc_reset. Fixes: 1cff7440 ("drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset.") Signed-off-by:
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Dmitry Baryshkov authored
Correct the CTL size on sm8450 platform. This fixes the incorrect merge of sm8350 support, which unfortunately also touched the SM8450 setup. Fixes: 0e91bcbb ("drm/msm/dpu: Add SM8350 to hw catalog") Signed-off-by:
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Dmitry Baryshkov authored
Use the values from the vendor DTs to set ubwc_swizzle in the catalog. Signed-off-by:
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Dmitry Baryshkov authored
The field ubwc_static was removed from struct dpu_mdp_cfg some time ago. Drop the corresponding kerneldoc now. Fixes: 544d8b96 ("drm/msm/dpu: update UBWC config for sm8150 and sm8250") Signed-off-by:
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