- 11 Jun, 2015 40 commits
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David S. Miller authored
Ivan Vecera says: ==================== bna: clean-up The patches clean the bna driver. v2: changes & comments requested by Joe ==================== Signed-off-by:David S. Miller <davem@davemloft.net>
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Ivan Vecera authored
...and remove some of them. It is not necessary to log when .probe() and .remove() are called or when TxQ is started or stopped. Also log level of some of them was changed to more appropriate one (link up/down, firmware loading failure. Signed-off-by:
Ivan Vecera <ivecera@redhat.com> Signed-off-by:
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Ivan Vecera authored
Timeout functions are defined with 'void *' ptr argument. They should be defined directly with 'struct bfa_ioc *' type to avoid type conversions. Signed-off-by:
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Ivan Vecera authored
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Ivan Vecera authored
Remove macros for manipulation with struct list_head and replace them with standard ones. Signed-off-by:
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Ivan Vecera authored
Pointer cmpl used to iterate through completion entries is updated at the beginning of while loop as well as at the end. The update at the end of the loop is useless. Signed-off-by:
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Ivan Vecera authored
Patch converts kzalloc->copy_from_user sequence to memdup_user. There is also one useless assignment of NULL to bnad->regdata as it is followed by assignment of kzalloc output. Signed-off-by:
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Ivan Vecera authored
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Ivan Vecera authored
TX_E_PRIO_CHANGE event is never sent for bna_tx so it doesn't need to be handled. After this change bna_tx->flags cannot contain BNA_TX_F_PRIO_CHANGED flag and it can be also eliminated. Signed-off-by:
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Ivan Vecera authored
The bna_rx_config struct member paused can be removed as it is never written and as it cannot have non-zero value the bna_rxf struct member flags also cannot have BNA_RXF_F_PAUSED value and is always zero. So the flags member can be removed as well as bna_rxf_flags enum and the code-paths that needs to have non-zero bna_rxf->flags. This clean-up makes bna_rxf_sm_paused state unsed and can be also removed. Signed-off-by: -
Ivan Vecera authored
RXF_E_PAUSE & RXF_E_RESUME events are never sent for bna_rxf object so they needn't to be handled. The bna_rxf's state bna_rxf_sm_fltr_clr_wait and function bna_rxf_fltr_clear are unused after this so remove them also. Signed-off-by:
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Ivan Vecera authored
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Ivan Vecera authored
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Ivan Vecera authored
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Ivan Vecera authored
removed: bna_rx_ucast_add bna_rx_ucast_del simplified: bna_enet_pause_config bna_rx_mcast_delall bna_rx_mcast_listset bna_rx_mode_set bna_rx_ucast_listset bna_rx_ucast_set Signed-off-by:
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Ivan Vecera authored
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Ivan Vecera authored
replaced macros: BNA_MAC_IS_EQUAL -> ether_addr_equal BNA_POWER_OF_2 -> is_power_of_2 BNA_TO_POWER_OF_2_HIGH -> roundup_pow_of_two removed unused macros: bfa_fsm_get_state bfa_ioc_clr_stats bfa_ioc_fetch_stats bfa_ioc_get_alt_ioc_fwstate bfa_ioc_isr_mode_set bfa_ioc_maxfrsize bfa_ioc_mbox_cmd_pending bfa_ioc_ownership_reset bfa_ioc_rx_bbcredit bfa_ioc_state_disabled bfa_sm_cmp_state bfa_sm_get_state bfa_sm_send_event bfa_sm_set_state bfa_sm_state_decl BFA_STRING_32 BFI_ADAPTER_IS_{PROTO,TTV,UNSUPP) BFI_IOC_ENDIAN_SIG BNA_{C,RX,TX}Q_PAGE_INDEX_MAX BNA_{C,RX,TX}Q_PAGE_INDEX_MAX_SHIFT BNA_{C,RX,TX}Q_QPGE_PTR_GET BNA_IOC_TIMER_FREQ BNA_MESSAGE_SIZE BNA_QE_INDX_2_PTR BNA_QE_INDX_RANGE BNA_Q_GET_{C,P}I BNA_Q_{C,P}I_ADD BNA_Q_FREE_COUNT BNA_Q_IN_USE_COUNT BNA_TO_POWER_OF_2 containing_rec Signed-off-by: -
Ivan Vecera authored
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Ivan Vecera authored
The patch converts mac_t type to widely used 'u8 [ETH_ALEN]'. Signed-off-by:
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Ivan Vecera authored
Parameters of all ether_addr_copy instances were checked for proper alignment. Alignment of bnad_bcast_addr is forced to 2 as the implicit alignment is 1. I have also renamed address parameter of bnad_set_mac_address() to addr. The name mac_addr was a little bit confusing as the real parameter is struct sockaddr *. v2: added __aligned directive to bnad_bcast_addr, renamed parameter of bnad_set_mac_address() (thx joe@perches.com) Signed-off-by: -
David S. Miller authored
Or Gerlitz says: ==================== mlx5 Ethernet driver update - Jun 11 2015 This series from Saeed, Achiad and Gal contains few fixes to the recently introduced mlx5 Ethernet functionality. ==================== Signed-off-by: -
Achiad Shochat authored
Allocate and use transport domain by the Ethernet driver code. Signed-off-by:
Achiad Shochat <achiad@mellanox.com> Signed-off-by:
Saeed Mahameed <saeedm@mellanox.com> Signed-off-by:
Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by:
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Achiad Shochat authored
Each transport object, namely TIR and TIS, must have a transport domain number (TDN) identifier. The driver wrongly assumed that it is OK to use TDN=0 without explicit TDN allocation from the device. The TDN will also be used for isolating different processes once user mode Ethernet will be supported. Signed-off-by:
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Saeed Mahameed authored
When NETIF_F_SG is set, each send WQE may have a different size since each skb can have different number of fragments as of LSO header etc. This implies that a given WQE may wrap around the send queue, i.e begin at its end and continue at its start. While it is legal by the device spec, we preferred a solution that avoids it - when building of current WQE is done, if the next WQE may wrap around the send queue, fill the send queue with NOPs WQEs till its end, so that the next WQE will begin at send queue start. NOP WQE for itself cannot wrap around the send queue since it is of minimal size - 64 bytes, and all send WQEs are a multiple of that size. Signed-off-by:
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Gal Pressman authored
The Ethernet driver requires at least 3 flow table levels to operate, enforce that. Signed-off-by:
Gal Pressman <galp@mellanox.com> Signed-off-by:
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Saeed Mahameed authored
We need to resolve a HW configuration issue for enabling HW CVLAN insertion. Meanwhile, no need to implement the VLAN insertion in the driver, rather use the generic kernel VLAN insertion method. Signed-off-by:
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Saeed Mahameed authored
Enable HW cacheline start padding and align RX WQE size to cacheline while considering HW start padding. Also, fix dma_unmap call to use the correct SKB data buffer size. Signed-off-by:
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Saeed Mahameed authored
Previously we configured HW MTU to be netdev->mtu, actually we need to configure netdev->mtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN). Also, query MTU can not fail, hence make the relevant helper a void functionm, add mlx5e_set_dev_port_mtu, helper function to handle MTU setting. Signed-off-by:
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Dan Carpenter authored
We return success if mlx5e_alloc_sq_db() fails but we should return an error code. Fixes: f62b8bb8 ('net/mlx5: Extend mlx5_core to support ConnectX-4 Ethernet functionality') Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Acked-by:
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Fabian Frederick authored
Use kernel.h macro definition. Thanks to Julia Lawall for Coccinelle scripting support. Signed-off-by:
Fabian Frederick <fabf@skynet.be> Signed-off-by:
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Fabian Frederick authored
Use kernel.h macro definition. Thanks to Julia Lawall for Coccinelle scripting support. Signed-off-by:
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Fabian Frederick authored
Use kernel.h macro definition. Thanks to Julia Lawall for Coccinelle scripting support. Signed-off-by:
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Fabian Frederick authored
Use kernel.h macro definition. Thanks to Julia Lawall for Coccinelle scripting support. Signed-off-by:
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Fabian Frederick authored
Use kernel.h macro definition. Thanks to Julia Lawall for Coccinelle scripting support. Signed-off-by:
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Geoff Levand authored
When the DEBUG preprocessor macro is defined the ps3_gelic_net driver build fails due to an undeclared routine gelic_descr_get_status(). This problem was introduced during the code cleanup of commit 6b0c21ce (net: Fix p3_gelic_net sparse warnings), which re-arranged the ordering of some of the gelic routines. This change just moves the gelic_descr_get_status() routine up in the ps3_gelic_net.c source file. There is no functional change. Fixes build errors like these: drivers/net/ethernet/toshiba/ps3_gelic_net.c: error: implicit declaration of function gelic_descr_get_status Signed-off-by:
Geoff Levand <geoff@infradead.org> Signed-off-by:
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Hadar Hen Zion authored
Add strings array of the current supported tunable options. Signed-off-by:
Hadar Hen Zion <hadarh@mellanox.com> Reviewed-by:
Amir Vadai <amirv@mellanox.com> Signed-off-by:
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David S. Miller authored
Florian Fainelli says: ==================== net: broadcom MDIO support for broken turn-around These two patches update the GENET and UniMAC MDIO controllers to deal with PHYs that are known to have a broken turn-around bug (e.g: BCM53125 and others) This utilizes the infrastructure that code recently added to do that in 'net-next'. Note that the changes look nearly identical and I will try to address the MDIO code duplication between GENET and UniMAC in a future patch series. Changes in v2: - remove brcmphy.h include in mdio-bcm-unimac.c - use the same comment as with GENET's MDIO read function ==================== Signed-off-by: -
Florian Fainelli authored
Some Ethernet PHYs/switches such as Broadcom's BCM53125 have a hardware bug which makes them not release the MDIO line during turn-around time. This gets flagged by the UniMAC MDIO controller as a read failure, and we fail the read transaction. Check the MDIO bus phy_ignore_ta_mask bitmask for the PHY we are reading from and if it is listed in this bitmask, ignore the read failure and proceed with returning the data we read out of the controller. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Florian Fainelli authored
Some Ethernet PHYs/switches such as Broadcom's BCM53125 have a hardware bug which makes them not release the MDIO line during turn-around time. This gets flagged by the GENET MDIO controller as a read failure, and we fail the read transaction. Check the MDIO bus phy_ignore_ta_mask bitmask for the PHY we are reading from and if it is listed in this bitmask, ignore the read failure and proceed with returning the data we read out of the controller. Signed-off-by:
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Gustavo Zacarias authored
Add PHY IDs for Davicom DM9161B and DM9161C variants. Tested with a DM9161C on a custom Atmel-based SAM9X25 board in RMII mode. The DM9161B uses the same model id with just the LSB bit of the version id changing (which is masked out). For all intents and purposes they're the same as the DM9161A with an added GPSI mode and better fabrication process. Signed-off-by:
Gustavo Zacarias <gustavo@zacarias.com.ar> Signed-off-by:
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