- 14 Jun, 2022 40 commits
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: c499d029 ("iio:dac: Add ad5755 driver") Signed-off-by:
Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by:
Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-51-jic23@kernel.org
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: 0357e488 ("iio:dac:ad5686: Refactor the driver") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 56ca9db8 ("iio: dac: Add support for the AD5592R/AD5593R ADCs/DACs") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 0dbe59c7 ("iio:ad5504: Do not store transfer buffers on the stack") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: 8341dc04 ("iio:dac: Add support for the ad5449") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: 5691b234 ("staging:iio:dac: Add AD5421 driver") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: a3e2940c ("staging:iio:dac: Add AD5360 driver") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: 6a17a076 ("iio:dac:ad5064: Add support for the ad5629r and ad5669r") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 50dd64d5 ("iio: common: ssp_sensors: Add sensorhub driver") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: e71d42e0 ("iio: amplifiers: New driver for AD8366 Dual-Digital Variable Gain Amplifier") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: fea251b6 ("iio: addac: add AD74413R driver") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: ac2bec9d ("iio: adc: tlc4541: add support for TI tlc4541 adc") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 3e87e783 ("iio: adc: Add TI ADS8688") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 8dd2d7c0 ("iio: adc: Add driver for the TI ADS8344 A/DC chips") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: 902c4b24 ("iio: adc: New driver for TI ADS7950 chips") Signed-off-by:
David Lechner <david@lechnology.com> Acked-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: d935eddd ("iio: adc: Add driver for Texas Instruments ADS131E0x ADC family") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: e717f8c6 ("iio: adc: Add the TI ads124s08 ADC code") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 4d671b71 ("iio: adc: ti-adc161s626: add support for TI 1-channel differential ADCs") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 913b8646 ("iio: adc: Add TI ADC128S052") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 50a6edb1 ("iio: adc: add ADC12130/ADC12132/ADC12138 ADC driver") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Dual fixes tags as two cases that were introduced in different patches. One of those patches is a fix however and likely to have been backported to stable kernels. Note the second alignment marking is likely to be unnecessary, but is left for now to keep this fix simple. Fixes: 3691e5a6 ("iio: adc: add driver for the ti-adc084s021 chip") Fixes: cbe5c697 ("iio: adc: ti-adc108s102: Fix alignment of buffer pushed to iio buffers.") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: 3691e5a6 ("iio: adc: add driver for the ti-adc084s021 chip") Signed-off-by:
Mårten Lindahl <marten.lindahl@axis.com> Link: https://lore.kernel.org/r/20220508175712.647246-30-jic23@kernel.org
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: efc945fb ("iio: adc: add support for ADC0831/ADC0832/ADC0834/ADC0838 chips") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Worth noting the fixes tag refers to the same issue being observed on a platform that probably had only 64 byte cachelines. Fixes: 0e81bc99 ("iio: mcp320x: Fix occasional incorrect readings") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 8a80a71d ("iio: adc: Add MAX1241 driver") Signed-off-by:
Alexandru Lazar <alazar@startmail.com> Acked-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: a9e9c715 ("iio: adc: add max1117/max1118/max1119 ADC driver") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: a8e7e88d ("iio: adc: Add Maxim MAX11100 driver") Signed-off-by:
Jacopo Mondi <jacopo@jmondi.org> Acked-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: fc167f62 ("iio: add support of the max1027") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: bc82222f ("iio:adc: Driver for Linear Technology LTC2497 ADC") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: e4c5c4df ("iio: adc: new driver to support Linear technology's ltc2496") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 72aa29ce ("iio: adc: hi8435: Holt HI-8435 threshold detector") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Note the fixes tag predates some changes to this line of code so automated application of this fix may fail. Fixes: 7f40e061 ("iio:adc:ad7949: Add AD7949 ADC driver family") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Note that some other fixes have applied to this line of code that may complicate automated backporting. Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes tag is clearly not where this was introduced but it is very unlikely anyone will back port it past that point. Fixes: 65dd3d3d ("staging:iio:ad7887: Squash everything into one file") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to reflect that separate cachelines 'may' be required. Fixes: a5f8c7da ("iio: adc: Add AD7768-1 ADC basic support") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to reflect the fact DMA safety 'may' require separate cachelines. Fixes: aa16c6bd ("iio:adc: Add support for AD7766/AD7767") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_ALIGN definition. Update the comment to reflect the fact DMA safety 'may' require separate cachelines. Fixes: 7989b4bb ("iio: adc: ad7616: Add support for AD7616 ADC") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to reflect that DMA safety 'may' require separate cachelines. Fixes tag is unlikely to be the actual introdution of the problem but is far enough back to cover any likely backporting. Fixes: 7a28fe3c ("staging:iio:ad7476: Squash driver into a single file.") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: be7fd3b8 ("iio:adc:ad7298 make the tx and rx buffers __be16") Signed-off-by:
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Jonathan Cameron authored
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 506d2e31 ("iio: adc: Add driver support for AD7292") Signed-off-by:
Marcelo Schmitt <marcelo.schmitt1@gmail.com> Acked-by:
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