- 17 Sep, 2012 4 commits
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Olof Johansson authored
Merge tag 'devel-omap-device-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc Kevin Hilman <khilman@ti.com>: Updates for omap_device layer for v3.7. Allows omap_device layer to keep track of driver bound status in order to make more intelligent decisions about idling unused devices. * tag 'devel-omap-device-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP: omap_device: idle devices with no driver bound ARM: OMAP: omap_device: don't attempt late suspend if no driver bound ARM: OMAP: omap_device: keep track of driver bound status + sync to 3.6-rc5
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Olof Johansson authored
Merge tag 'tegra-for-3.7-cpu-hotplug' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: implement CPU hotplug This branch implements CPU hot-plugging support for both Tegra20 and Tegra30. Portions of the implementation are contained in the clock driver, hence this branch is based on the common clock conversion in order to avoid duplicating work. By Joseph Lo via Stephen Warren * tag 'tegra-for-3.7-cpu-hotplug' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra20: add CPU hotplug support ARM: tegra30: add CPU hotplug support ARM: tegra: clean up the common assembly macros into sleep.h ARM: tegra: replace the CPU CAR access code by tegra_cpu_car_ops ARM: tegra: introduce tegra_cpu_car_ops structures
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Olof Johansson authored
Merge tag 'tegra-for-3.7-common-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: switch to the common clock framework This branch contains a few bug-fixes, followed by a conversion of Tegra's clock driver to the common clock framework, followed by various bug fixes found after the conversion. * tag 'tegra-for-3.7-common-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: Tegra: Add smp_twd clock for Tegra20 ARM: tegra: cpu-tegra: explicitly manage re-parenting ARM: tegra: fix overflow in tegra20_pll_clk_round_rate() ARM: tegra: Fix data type for io address ARM: tegra: remove tegra_timer from tegra_list_clks ARM: tegra30: clocks: fix the wrong tegra_audio_sync_clk_ops name ARM: tegra: clocks: separate tegra_clk_32k_ops from Tegra20 and Tegra30 ARM: tegra: Remove duplicate code ARM: tegra: Port tegra to generic clock framework ARM: tegra: Add clk_tegra structure and helper functions ARM: tegra: Rename tegra20 clock file ARM: tegra20: Separate out clk ops and clk data ARM: tegra30: Separate out clk ops and clk data ARM: tegra: fix U16 divider range check ARM: tegra: turn on UART A clock at boot
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git://git.pengutronix.de/git/imx/linux-2.6Olof Johansson authored
ARM i.MX SoC updates * tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6: ARM: i.MX35: Implement camera and keypad clocks ARM: mxc: ssi-fiq: Make ssi-fiq.S Thumb-2 compatible ARM i.MX53: register CAN clocks arm imx31: add a few pinmux settings the tt01 needs
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- 13 Sep, 2012 7 commits
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Joseph Lo authored
Hotplug function put CPU in offline or online mode at runtime. When the CPU been put into offline, it was been clock gated. The offline CPU can be power gated, when the remaining CPU goes into LP2. Based on the worked by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
Hotplug function put CPUs in offline or online state at runtime. When the CPU been put in the offline state, it was been clock and power gated. Except primary CPU other CPUs can be hotplugged. Based on the work by: Scott Williams <scwilliams@nvidia.com> Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
There are some common macros for Tegra low-level assembly code. Clean up them into one header file and move the definitions that will be re-used into it as well. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
Replacing the code that directly access to CAR registers with tegra_cpu_car_ops. This ops hides CPU CAR access inside and provides control interface for it. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
The tegra_cpu_car_ops provide the interface for CPU to control it's clock gating and reset status. The other drivers should use this for CPU control. And should not directly access CAR registers to control CPU. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Clockevent's frequency is changed upon cpufreq change notification. It fetches local timer's rate to update the clockevent frequency. This patch adds local timer clock for Tegra20. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Tony Lindgren authored
Merge tag 'for_3.7-omap_device' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into devel-omap-device Updates for omap_device layer for v3.7. Allows omap_device layer to keep track of driver bound status in order to make more intelligent decisions about idling unused devices.
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- 12 Sep, 2012 5 commits
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Kevin Hilman authored
Under some circumstances, drivers may leave an omap_device enabled due to driver programming errors, or due to a failure in the drivers probe method. Using the recently added omap_device driver_status field, we can detect conditions where an omap_device is enabled but has no driver bound and then ensure that the device is properly idled until it can be probed again. The goal of this feature is not only to detect and warn on these error conditions, but also to ensure that devices are properly put in low-power states so they do not prevent SoC-wide low-power states. Reviewed-by:
Paul Walmsley <paul@pwsan.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Kevin Hilman authored
Currently, the omap_device PM domain layer uses the late suspend and early resume callbacks to ensure devices are in their low power states. However, this is attempted even in cases where a driver probe has failed. If a driver's ->probe() method fails, the driver is likely in a state where it is not expecting its runtime PM callbacks to be called, yet currently the omap_device PM domain code attempts to call the drivers callbacks. To fix, use the omap_device driver_status field to check whether a driver is bound to the omap_device before attempting to trigger driver callbacks. Reviewed-by:
Paul Walmsley <paul@pwsan.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Kevin Hilman authored
Use the bus notifier to keep track of driver bound status by adding a new internal field to struct omap_device: _driver_status. This will be useful for follow-up patches which need to know whether or not a driver is bound in order to make intelligent omap_device enable/idle decisions. Reviewed-by:
Paul Walmsley <paul@pwsan.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Olof Johansson authored
* renesas/pmu: ARM: shmobile: emev2: enable PMU(Performance Monitoring Unit) ARM: shmobile: sh73a0: enable PMU(Performance Monitoring Unit)
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesasOlof Johansson authored
* 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: r8a7779: add SDHI clock support
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- 11 Sep, 2012 4 commits
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Stephen Warren authored
When changing a PLL's rate, it must have no active children. The CPU clock cannot be stopped, and CPU clock's divider is not used. The old clock driver used to handle this by internally reparenting the CPU clock onto a different PLL when changing the CPU clock rate. However, the new common-clock based clock driver does not do this, and probably cannot do this due to the locking issues it would cause. To solve this, have the Tegra cpufreq driver explicitly perform the reparenting operations itself. This is probably reasonable anyway, since such reparenting is somewhat a matter of policy (e.g. which alternate clock source to use, whether to leave the CPU clock a child of the alternate clock source if it's running at the desired rate), and hence is something more appropriate for the cpufreq driver than the core clock driver anyway. Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
32-bit math isn't enough when e.g. *prate=12000000, and sel->n=1000. Use 64-bit math to prevent this. Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Tetsuyuki Kobayashi authored
This patch enables PMU(Performance Monitoring Unit) for emev2. Signed-off-by:
Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by:
Simon Horman <horms@verge.net.au>
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Tetsuyuki Kobayashi authored
This patch enables PMU(Performance Monitoring Unit) for sh73a0. Signed-off-by:
Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by:
Simon Horman <horms@verge.net.au>
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- 08 Sep, 2012 3 commits
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Linus Torvalds authored
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git://git.linaro.org/people/mszyprowski/linux-dma-mappingLinus Torvalds authored
Pull DMA-mapping fixes from Marek Szyprowski: "Another set of fixes for ARM dma-mapping subsystem. Commit e9da6e99 replaced custom consistent buffer remapping code with generic vmalloc areas. It however introduced some regressions caused by limited support for allocations in atomic context. This series contains fixes for those regressions. For some subplatforms the default, pre-allocated pool for atomic allocations turned out to be too small, so a function for setting its size has been added. Another set of patches adds support for atomic allocations to IOMMU-aware DMA-mapping implementation. The last part of this pull request contains two fixes for Contiguous Memory Allocator, which relax too strict requirements." * 'fixes-for-3.6' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping: ARM: dma-mapping: IOMMU allocates pages from atomic_pool with GFP_ATOMIC ARM: dma-mapping: Introduce __atomic_get_pages() for __iommu_get_pages() ARM: dma-mapping: Refactor out to introduce __in_atomic_pool ARM: dma-mapping: atomic_pool with struct page **pages ARM: Kirkwood: increase atomic coherent pool size ARM: DMA-Mapping: print warning when atomic coherent allocation fails ARM: DMA-Mapping: add function for setting coherent pool size from platform code ARM: relax conditions required for enabling Contiguous Memory Allocator mm: cma: fix alignment requirements for contiguous regions
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git://git.kernel.org/pub/scm/linux/kernel/git/dtor/inputLinus Torvalds authored
Pull input subsystem updates from Dmitry Torokhov. * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input: Input: wacom - add support for EMR on Cintiq 24HD touch Input: i8042 - add Gigabyte T1005 series netbooks to noloop table Input: imx_keypad - reset the hardware before enabling Input: edt-ft5x06 - fix build error when compiling wthout CONFIG_DEBUG_FS
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- 07 Sep, 2012 6 commits
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git://git.antcom.de/linux-2.6Olof Johansson authored
* 'lpc32xx/core' of git://git.antcom.de/linux-2.6: ARM: LPC32xx: Remove board specific GPIO init ARM: LPC32xx: Provide DMA filter callbacks via platform data ARM: LPC32xx: Use handle_edge_irq() callback on edge type irqs + sync to 3.6-rc4
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git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hidLinus Torvalds authored
Pull HID updates from Jiri Kosina: "It contains a fix for Eaton Ellipse MAX UPS from Alan Stern, performance improvement (not processing debug data if noone is interested), by Henrik Rydberg, and allowing tpkbd-driven devices to work even with generic driver in a crippled mode, by Andres Freund." * 'upstream-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid: HID: tpkbd: work even if the new Lenovo Keyboard driver is not configured HID: Only dump input if someone is listening HID: add NOGET quirk for Eaton Ellipse MAX UPS
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Prashant Gaikwad authored
Warnings were generated because following commit changed data type for address pointer 195bbca ARM: 7500/1: io: avoid writeback addressing modes for __raw_ accessors arch/arm/mach-tegra/tegra30_clocks.c: In function 'clk_measure_input_freq': arch/arm/mach-tegra/tegra30_clocks.c:418:2: warning: passing argument 2 of '__raw_writel' makes pointer from integer without a cast .../arch/arm/include/asm/io.h:88:20: note: expected 'volatile void *' but argument is of type 'unsigned int Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Andres Freund authored
c1dcad2d added a new driver configured by HID_LENOVO_TPKBD but made the hid_have_special_driver entry non-optional which lead to a recognized but non-working device if the new driver wasn't configured (which is the correct default). Signed-off-by:
Andres Freund <andres@anarazel.de> Signed-off-by:
Jiri Kosina <jkosina@suse.cz>
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Linus Torvalds authored
Merge tag 'stable/for-linus-3.6-rc4-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen Pull Xen bug-fixes from Konrad Rzeszutek Wilk: * Fix for TLB flushing introduced in v3.6 * Fix Xen-SWIOTLB not using proper DMA mask - device had 64bit but in a 32-bit kernel we need to allocate for coherent pages from a 32-bit pool. * When trying to re-use P2M nodes we had a one-off error and triggered a BUG_ON check with specific CONFIG_ option. * When doing FLR in Xen-PCI-backend we would first do FLR then save the PCI configuration space. We needed to do it the other way around. * tag 'stable/for-linus-3.6-rc4-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen: xen/pciback: Fix proper FLR steps. xen: Use correct masking in xen_swiotlb_alloc_coherent. xen: fix logical error in tlb flushing xen/p2m: Fix one-off error in checking the P2M tree directory.
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git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pciLinus Torvalds authored
Pull PCI updates from Bjorn Helgaas: "Power management - PCI/PM: Enable D3/D3cold by default for most devices - PCI/PM: Keep parent bridge active when probing device - PCI/PM: Fix config reg access for D3cold and bridge suspending - PCI/PM: Add ABI document for sysfs file d3cold_allowed Core - PCI: Don't print anything while decoding is disabled" * tag '3.6-pci-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: Don't print anything while decoding is disabled PCI/PM: Add ABI document for sysfs file d3cold_allowed PCI/PM: Fix config reg access for D3cold and bridge suspending PCI/PM: Keep parent bridge active when probing device PCI/PM: Enable D3/D3cold by default for most devices
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- 06 Sep, 2012 11 commits
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Stephen Warren authored
tegra_time is a struct sys_timer, not a struct clk, so can't be included in an array of struct clk *. Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
It should use tegra30_audio_sync_clk_ops for tegra30. It will cause the tegra30 use the wrong audio_sync_clk_ops when build a kernel with a tegra20 and tegra30 both supported kernel. And building error when a tegra30-only kernel. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Joseph Lo authored
Currently the tegra20 and tegra30 share the same symbol for tegra_clk_32k_ops. This will cause a compile error when building a tegra20-only kernel image. Add tegra_clk_32k_ops for tegra20 and modify tegra30_clk_32k_ops for tegra30. Signed-off-by:
Joseph Lo <josephl@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Remove Tegra legacy clock framework code. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
This patch converts tegra clock code to generic clock framework in following way: - Implement clk_ops as required by generic clk framework. (tegraXX_clocks.c) - Use platform specific struct clk_tegra in clk_ops implementation instead of struct clk. - Initialize all clock data statically. (tegraXX_clocks_data.c) Legacy framework did not have recalc_rate and is_enabled functions. Implemented these functions. Removed init function. It's functionality is splitted into recalc_rate and is_enabled. Static initialization is used since slab is not up in .init_early and clock is needed to be initialized before clockevent/clocksource initialization. Macros redefined for clk_tegra. Also, single struct clk_tegra is used for all type of clocks (PLL, peripheral etc.). This is to move quickly to generic common clock framework so that other dependent features will not be blocked (such as DT binding). Enabling COMMON_CLOCK config moved to ARCH_TEGRA since it is enabled for both Tegra20 and Tegra30. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Add Tegra platform specific clock structure clk_tegra and some helper functions for generic clock framework. struct clk_tegra is the single strcture used for all types of clocks. reset and cfg_ex ops moved to clk_tegra from clk_ops. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Make the name consistent with other files. s/tegra2/tegra20 Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Move clock initialization data to separate file. This is required for migrating to generic clock framework if static initialization is used. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Move clock initialization data to separate file. This is required for migrating to generic clock framework if static initialization is used. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
A U16 divider can divide a clock by 1..64K. However, the range-check in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's downstream kernels already have the fixed range-check. In practice this is a problem on Whistler's I2C bus, which uses a bus clock rate of 100KHz (rather than the more common 400KHz on Tegra boards), which requires a HW module clock of 8*100KHz. The parent clock is 216MHz, leading to a desired divider of 270. Prior to conversion to the common clock framework, this range error was somehow ignored/irrelevant and caused no problems. However, the common clock framework evidently has more rigorous error-checking, so this failure causes the I2C bus to fail to operate correctly. Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
Some boards use UART D for the main serial console, and some use UART A. UART D's clock is listed in board-dt-tegra20.c's clock table, whereas UART A's clock is not. This causes the clock code to think UART A's clock is unsed. The common clock framework turns off unused clocks at boot time. This makes the kernel appear to hang. Add UART A's clock into the clock table to prevent this. Eventually, this requirement should be handled by the UART driver, and/or properties in a board-specific device tree file. Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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