- 18 Mar, 2015 27 commits
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Guenter Roeck authored
Fix the following build failure: In file included from drivers/pinctrl/mediatek/pinctrl-mt8135.c:24:0: drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h:19:32: fatal error: pinctrl-mtk-common.h: No such file or directory seen when building arm:multi_v7_defconfig. Fixes: 94097d89c145 ("pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.") Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by:Guenter Roeck <linux@roeck-us.net> Reviewed-by:
Paul Walmsley <paul@pwsan.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Geert Uytterhoeven authored
The r8a7790 platform is now DT-only, the driver doesn't need to match platform devices by name anymore. Remove the corresponding platform_device_id entry. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Geert Uytterhoeven authored
The emev2 platform is now DT-only, the driver doesn't need to match platform devices by name anymore. Remove the corresponding platform_device_id entry. Signed-off-by:
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Geert Uytterhoeven authored
Currently all PFC registers lie in low 32-bit address space. Hence use u32 instead of unsigned long to store PFC register addresses in pinctrl tables. All calculations of virtual addresses use a phys_addr_t intermediate, so we know where to add an offset if the 32-bit assumption ever becomes false. While this doesn't impact 32-bit builds, it would save ca. 7 KiB on a 64-bit shmobile_defconfig kernel. Signed-off-by:
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Geert Uytterhoeven authored
All other loops over sh_pfc_soc_info.data_regs[] use pinmux_data_reg.regwidth as the sentinel, which is safer as zero is never a valid regwidth value (reg could be zero if we start using it to store an offset). Signed-off-by:
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Geert Uytterhoeven authored
As register and field widths and offsets are in the range 1..32, use unsigned int (mostly replacing unsigned long) to store them in local variables and for passing them around. Move to one variable per line, move variables to the beginning of the block where they are used, and drop superfluous initializations while we are at it. Signed-off-by:
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Geert Uytterhoeven authored
Register and field widths are in the range 1..32. Storing them in the pinctrl data in (arrays of) unsigned long wastes space. This decreases the size of a (32-bit) shmobile_defconfig kernel supporting 7 SoCs by 26460 bytes. Signed-off-by:
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Ken Xue authored
KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM. Current driver patch only support GPIO in x86. Signed-off-by:
Ken Xue <Ken.Xue@amd.com> [Moved back to <linux/gpio.h> header] Signed-off-by:
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Baruch Siach authored
Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Signed-off-by:
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Baruch Siach authored
The callback function signature has changed in commit a5818a8b (pinctrl: get_group_pins() const fixes) Fixes: a5818a8b ('pinctrl: get_group_pins() const fixes') Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by:
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Abhilash Kesavan authored
The alive pin controller on exynos7 does not support external gpio interrupts. Hence, remove the eint_gpio_init call-back for it. This fixes the following error message seen during exynos7 boot-up: "samsung-pinctrl 10580000.pinctrl: irq number not available" Signed-off-by:
Abhilash Kesavan <a.kesavan@samsung.com> Acked-by:
Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by:
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Ray Jui authored
This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO controller, the chipCommonG GPIO controller, and the always-on GPIO controller. Basic PINCONF configurations such as bias pull up/down, and drive strength are also supported in this driver. Pins from the ASIU GPIO controller can be individually muxed to GPIO function, through interaction with the Cygnus IOMUX controller Signed-off-by:
Ray Jui <rjui@broadcom.com> Reviewed-by:
Scott Branden <sbranden@broadcom.com> Tested-by:
Dmitry Torokhov <dtor@chromium.org> Signed-off-by:
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Ray Jui authored
Document the GPIO/PINCONF device tree binding for Broadcom Cygnus SoC Signed-off-by:
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Baruch Siach authored
Make the example code consistent wrt local function and struct definitions. Signed-off-by:
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Baruch Siach authored
This API has changed in commit 6e5e959d (pinctrl: API changes to support multiple states per device). Fixes: 6e5e959d ('pinctrl: API changes to support multiple states per device') Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by:
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Baruch Siach authored
Commit 03e9f0ca (pinctrl: clean up after enable refactoring) updated the documentation to remove mention of disable(), and rename enable() to set_mux(). One in-text mention was forgotten. Fix this. Fixes: 03e9f0ca ('pinctrl: clean up after enable refactoring') Signed-off-by:
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Hongzhou Yang authored
Due to pinconf_generic_parse_dt_config() API changes in pinctrl devel branch, add one parameter to fix build error. Also fix warning: drivers/pinctrl/mediatek/pinctrl-mtk-common.c:718:3: warning: too many arguments for format [-Wformat-extra-args] dev_err(&pdev->dev, "only support pins-are-numbered format\n", ret); ^ by removing extra parameter when calling dev_err in mtk_pctrl_init. Signed-off-by:Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by:
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Yingjoe Chen authored
MTK EINT does not support generating interrupt on both edges. Emulate this by changing edge polarity while enable irq, set types and interrupt handling. This follows an example of drivers/gpio/gpio-mxc.c. Signed-off-by:
Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by:
Chaotian Jing <chaotian.jing@mediatek.com> Acked-by:
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Hongzhou Yang authored
Add mt8173 support using mediatek common pinctrl driver. MT8173 have a different ies_smt setting register than mt8135, so adding this support to common code. Signed-off-by:
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Maoguang Meng authored
MTK SoC support external interrupt(EINT) from most SoC pins. Add EINT support to pinctrl driver. Signed-off-by:
Maoguang Meng <maoguang.meng@mediatek.com> Signed-off-by:
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Hongzhou Yang authored
The mediatek SoCs have GPIO controller that handle both the muxing and GPIOs. The GPIO controller have pinmux, pull enable, pull select, direction and output high/low control. This driver include common driver and mt8135 part. The common driver include the pinctrl driver and GPIO driver. The mt8135 part contain its special device data. Signed-off-by:
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Hongzhou Yang authored
Add devicetree bindings for Mediatek SoC pinctrl driver. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
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Geert Uytterhoeven authored
As PFC registers are either 8, 16, or 32 bits wide, use u32 (mostly replacing unsigned long) to store (parts of) register values and masks. Switch the shadow register operations from {set,clear}_bit() to plain C bit operations, as the former can operate on long data only. Signed-off-by: -
Ray Jui authored
This adds the initial driver support for the Broadcom Cygnus IOMUX controller. The Cygnus IOMUX controller supports group based mux configuration but allows certain pins to be muxed to GPIO individually Signed-off-by:
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Ray Jui authored
Device tree binding documentation for Broadcom Cygnus IOMUX driver Signed-off-by:
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Ray Jui authored
Consolidate Broadcom pinctrl drivers into drivers/pinctrl/bcm/* Signed-off-by:
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Stefan Agner authored
Commit 3dac1918 ("pinctrl: imx: detect uninitialized pins") needs the values in struct imx_pin_reg to be -1. This has been done in a rather unorthodox way by setting the memory to 0xff using memset... Use a proper for loop to initialize the whole array with -1. Signed-off-by:
Stefan Agner <stefan@agner.ch> Acked-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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- 09 Mar, 2015 13 commits
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Stanimir Varbanov authored
This enables support of 'input-enable' pinconf generic property in the pinctrl driver. Signed-off-by:
Stanimir Varbanov <svarbanov@mm-sol.com> Acked-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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Stanimir Varbanov authored
This makes the pinctrl driver to use the generic pinconf interface. Mainly it gives us a way to use debugfs to dump group configurations. Signed-off-by:
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Baruch Siach authored
There is no code ender the 'err' label. Just return the error code directly. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by:
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Baruch Siach authored
struct pinctrl_desc does not contain the maxpin member since commit 0d2006bb (pinctrl: remove unnecessary max pin number). Fixes: 0d2006bb ('pinctrl: remove unnecessary max pin number') Signed-off-by:
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Colin Ian King authored
Fix typo, "flaged" -> "flagged" Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Stephen Warren authored
Tegra210's pinmux supports a different set of pins/options than earlier SoCs, so requires its own driver (well, table of pin-specific data). Cc: devicetree@vger.kernel.org Signed-off-by:
Stephen Warren <swarren@nvidia.com> Tested-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
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Stephen Warren authored
Both nvidia,io-hv and nvidia,rcv-sel represent the fact that a particular pin's IO buffers are configured to accept "high voltage" input signals. The TRM for different chips names the register field rcv-sel on older SoCs and io_hv on newer SoCs. Add the new naming option into the pinctrl driver so that DT files can use naming consistent with the TRM. This new property name will be documented in the patch that adds support for the new SoC. Signed-off-by:
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Stephen Warren authored
Some of the pinmux configuration bits that exist in "drive group" registers in Tegra30..Tegra124 move to the "pinmux" registers on future chips. Add a flag to support this. Signed-off-by:
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Stephen Warren authored
Various non-semantic tweaks and layout/consistency fixes for existing Tegra pinctrl drivers. Move the definition of DRV_PINGROUP_REG() before the definition of PINGROUP() so that a future SoC driver can invoke the former from the latter. PINGROUP_BIT_Y(n) is just n, so replace it with n. Re-wrap the parameters to *PINGROUP(). Keep various enums sorted in the Tegra124 driver. Various white-space consistency fixes. These changes aim to update existing drivers to be consistent with future SoC drivers. While we could ignore these tweaks to the existing drivers, I'd like to keep everything as consistent as possible for easy comparison. Besides, I auto-generate the drivers, and maintaining special-cases to keep the differences in place is annoying. Signed-off-by:
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Baruch Siach authored
Signed-off-by:
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Thomas Petazzoni authored
This commit adds the Device Tree binding documentation to describe the pin-muxing controller of the Marvell Armada 39x processors. Two variants are supported for the moment: the 88F6920 (Armada 390) and 88F6928 (Armada 398). Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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Sanjeev Sharma authored
Make of_device_id array const. Signed-off-by:
Sanjeev Sharma <Sanjeev_Sharma@mentor.com> Signed-off-by:
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Geert Uytterhoeven authored
After the last user of the in_pd/in_pu bias parameters of the _PCRH() macro was removed in commit 80da8e02 ("sh-pfc: r8a7740: Add bias (pull-up/down) pinconf support"), bias parameters are supposed to be configured using the generic pinctl mechanism, which calls the .set_bias() method. However, the PORTCR() macro still represents the control register as consisting of two 4-bit fields. Hence the bias configuration in the uppermost 2 bits is always overwritten with zeroes when a pin is configured for GPIO, disabling any previously configured bias. Use the variable config register macro instead, to represent the register as having 4 fields, and to make sure only the input/output control and function fields are touched. This affects R-Mobile APE6 (r8a73a4), R-Mobile A1 (r8a7740), SH-Mobile AP4 (sh7372), and SH-Mobile AG5 (sh73a0). Signed-off-by:
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