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  1. 27 Oct, 2015 19 commits
  3. 23 Oct, 2015 2 commits
    • Scott Wood's avatar
      clk: qoriq: Fix wrong data in p2041_cmux_grp2 · 2c7693e0
      Scott Wood authored 
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      2c7693e0
    • Scott Wood's avatar
      powerpc/85xx: Load all early TLB entries at once · d9e1831a
      Scott Wood authored 
      Use an AS=1 trampoline TLB entry to allow all normal TLB1 entries to
be loaded at once.  This avoids the need to keep the translation that
code is executing from in the same TLB entry in the final TLB
configuration as during early boot, which in turn is helpful for
relocatable kernels (e.g. kdump) where the kernel is not running from
what would be the first TLB entry.

On e6500, we limit map_mem_in_cams() to the primary hwthread of a
core (the boot cpu is always considered primary, as a kdump kernel
can be entered on any cpu).  Each TLB only needs to be set up once,
and when we do, we don't want another thread to be running when we
create a temporary trampoline TLB1 entry.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      d9e1831a
  5. 21 Oct, 2015 3 commits
    • Scott Wood's avatar
      clk: qoriq: Add ls2080a support. · 9e19ca2f
      Scott Wood authored 
      LS2080A is the first implementation of the chassis 3 clockgen, which
has a different register layout than previous chips.  It is also little
endian, unlike previous chips.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      9e19ca2f
    • Scott Wood's avatar
      clk: qoriq: Move chip-specific knowledge into driver · 0dfc86b3
      Scott Wood authored 
      The device tree should describe the chips (or chip-like subblocks) in
the system, but it generally does not describe individual registers --
it should identify, rather than describe, a programming interface.

This has not been the case with the QorIQ clockgen nodes.  The
knowledge of what each bit setting of CLKCnCSR means is encoded in
three places (binding, pll node, and mux node), and the last also needs
to know which options are valid on a particular chip.  All three of
these locations are considered stable ABI, making it difficult to fix
mistakes (of which I have found several), much less refactor the
abstraction to be able to address problems, limitations, or new chips.

Under the current binding, a pll clock specifier of 2 means that the
PLL is divided by 4 -- and the driver implements this, unless there
happen to be four clock-output-names rather than 3, in which case it
interprets it as PLL divided by 3.  This does not appear in the binding
documentation at all.  That hack is now considered stable ABI.

The current device tree nodes contain errors, such as saying that
T1040 can set a core clock to PLL/4 when only PLL and PLL/2 are options.
The current binding also ignores some restrictions on clock selection,
such as p5020's requirement that if a core uses the "wrong" PLL, that
PLL must be clocked lower than the "correct" PLL and be at most 80% of
the rated CPU frequency.

Possibly because of the lack of the ability to express such nuance in
the binding, some valid options are omitted from the device trees, such
as the ability on p4080 to run cores 0-3 from PLL3 and cores 4-7 from
PLL1 (again, only if they are at most 80% of rated CPU frequency).
This omission, combined with excessive caution in the cpufreq driver
(addressed in a subsequent patch), means that currently on a 1500 MHz
p4080 with typical PLL configuration, cpufreq can lower the frequency
to 1200 MHz on half the CPUs and do nothing on the others.  With this
patchset, all CPUs can be lowered to 1200 MHz on a rev2 p4080, and on a
rev3 p4080 half can be lowered to 750 MHz and the other half to 600
MHz.

The current binding only deals with CPU clocks.  To describe FMan in
the device tree, we need to describe its clock.  Some chips have
additional muxes that work like the CPU muxes, but are not described in
the device tree.  Others require inspecting the Reset Control Word to
determine which PLL is used.  Rather than continue to extend this mess,
replace it.  Have the driver bind to the chip-specific clockgen
compatible, and keep the detailed description of quirky chip variations
in the driver, where it can be easily fixed, refactored, and extended.

Older device trees will continue to work (including a workaround for
old ls1021a device trees that are missing compatible and reg in the
clockgen node, which even the old binding required).  The pll/mux
details in old device trees will be ignored, but "clocks" properties
pointing at the old nodes will still work, and be directed at the
corresponding new clock.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      0dfc86b3
    • Scott Wood's avatar
      powerpc/fsl: Move fsl_guts.h out of arch/powerpc · 94848654
      Scott Wood authored 
      Freescale's Layerscape ARM chips use the same structure.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      94848654
  7. 17 Oct, 2015 10 commits
  9. 16 Oct, 2015 3 commits
  11. 15 Oct, 2015 3 commits
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