- 23 Jan, 2014 11 commits
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David Daney authored
This will be needed by the next patch to use said nodes for probing via the device tree. Signed-off-by:
David Daney <david.daney@cavium.com> Tested-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by:
John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6185/
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Paul Burton authored
This patch switches Malta from using the MIPS implementation of early printk with Malta's prom_putchar to using the generic 8250_early implementation. This offers a couple of advantages: - We duplicate less generic code. - The UART can be initialised rather than being reliant upon inheriting a valid setup from the bootloader. The Malta console_config function is extended to initialise the early console if no earlycon= kernel parameter is provided, inheriting the modetty0 bootloader environment if present and falling back to a default 38400n8r setup if not. This matches the behaviour used for the regular console= parameter. Signed-off-by:Paul Burton <paul.burton@imgtec.com> Reviewed-by:
Markos Chandras <markos.chandras@imgtec.com> Reviewed-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Paul Burton authored
This patch causes the kernel to mux the SERIRQ interrupt to the SERIRQ pin of the PIIX4 and to enable that interrupt. The kernel depends upon the interrupt when using the SuperIO UARTs (ttyS0 & ttyS1) but previously would not configure it, instead relying upon the bootloader having done so. If that is not the case then the typical result is that the system appears to hang once it reaches userland as no output is displayed on the UART. Signed-off-by:
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Paul Burton authored
The RTC is used on Malta to estimate the clock frequency of the CPU & optionally the GIC. However the kernel previously did not initialise the RTC, instead relying upon the bootloader having done so. In order to minimise dependencies which the kernel has upon the bootloader this patch causes the kernel to initialise the RTC itself prior to making use of it. Signed-off-by:
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Paul Burton authored
This variable seems to have been copied from Malta when SEAD3 support was introduced, but is likewise unused. Remove it. Signed-off-by:
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Paul Burton authored
This variable was introduced by commit 96348c8f (of Ralf's historic Linux/MIPS repository) "Remaining fixes for MIPS's eval boards." but I don't see any use of it either then or now. Remove it. Signed-off-by:
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Aaro Koskinen authored
Export symbols needed by the octeon-ethernet driver. The patch fixes a build failure with CONFIG_OCTEON_ETHERNET=m. Signed-off-by:
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Guenter Roeck authored
The following build error is seen if CONFIG_32BIT is undefined, CONFIG_64BIT is defined, and CONFIG_MIPS32_O32 is undefined. asm/syscall.h: In function 'mips_get_syscall_arg': arch/mips/include/asm/syscall.h:32:16: error: unused variable 'usp' [-Werror=unused-variable] cc1: all warnings being treated as errors Fixes: c0ff3c53 ('MIPS: Enable HAVE_ARCH_TRACEHOOK') Signed-off-by:
Guenter Roeck <linux@roeck-us.net> Acked-by:
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Aaro Koskinen authored
The boot hangs early on EBH5600 board when octeon_fdt_pip_iface() is trying enumerate a non-existant interface. The actual hang happens in cvmx_helper_interface_get_mode(): mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); when interface == 4. We can avoid this situation by first checking that the interface exists in the DTB. Signed-off-by:
Aaro Koskinen <aaro.koskinen@nsn.com> Acked-by:
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Aaro Koskinen authored
When booting with in-kernel DTBs, the pruning code will enumerate interfaces 0-4. However, there is memory reserved only for 4 so some other data will get overwritten by cvmx_helper_interface_enumerate(). Signed-off-by:
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Antony Pavlov authored
Signed-off-by:
Antony Pavlov <antonynpavlov@gmail.com> Acked-by:
Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
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- 22 Jan, 2014 29 commits
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Felix Fietkau authored
Only one MIPS development board actually supports enabling/disabling DMA coherency at runtime, so it's not a good idea to push the overhead of checking that configuration setting onto every other supported target as well. Signed-off-by:
Felix Fietkau <nbd@openwrt.org> Signed-off-by:
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Steven J. Hill authored
Clean-up code according to the 'checkpatch.pl' script. Signed-off-by:
Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by:
Qais Yousef <Qais.Yousef@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6097/Reviewed-by:
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Deng-Cheng Zhu authored
Malta with multi-core CM platforms can now use APRP functionality. Signed-off-by:
Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by:
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Deng-Cheng Zhu authored
This patch adds RTLX API support for platforms having a CMP. Signed-off-by:
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Deng-Cheng Zhu authored
Split the RTLX functionality in preparation for adding support for CMP platforms. Common functions remain in the original file and a new file contains code specific to platforms that do not have a CMP. Signed-off-by:
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Deng-Cheng Zhu authored
This patch adds VPE loader support for platforms having a CMP. Signed-off-by:
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Deng-Cheng Zhu authored
Split the VPE functionality in preparation for adding support for CMP platforms. Common functions remain in the original file and a new file contains code specific to platforms that do not have a CMP present. Signed-off-by:
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Steven J. Hill authored
This patch accomplishes the following: * Clean up wording on all MIPS MT configuration menu items. * Simplify and neaten up options selected by MIPS_MT_SMP. * Make MIPS_MT_SMTC support as deprecated. * Make MIPS_CMP support to depend on MIPS_MT_SMP also. * Remove redundant options selected by MIPS_CMP. Signed-off-by:
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Leonid Yegoshin authored
Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
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Leonid Yegoshin authored
The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by:
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Leonid Yegoshin authored
Add processor identifiers for UP and MT interAptiv processors. Signed-off-by:
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Steven J. Hill authored
Add a new mips/segments debugfs file to print the 6 segmentation control registers for supported cores. A sample from a proAptiv core is given below: Signed-off-by:
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Leonid Yegoshin authored
The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by:
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Leonid Yegoshin authored
The TLBINVF instruction can be used to flush the entire VTLB. This eliminates the need for the TLBWI loop and improves performance. Reviewed-by:
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Leonid Yegoshin authored
Signed-off-by:
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Leonid Yegoshin authored
Signed-off-by:
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Leonid Yegoshin authored
The proAptiv Multiprocessing System is a power efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The proAptiv Multiprocessing System combines a deep pipeline with multi-issue out of order execution for improved computational throughput. The proAptiv Multiprocessing System can contain one to six MIPS32r3 proAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by:
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Leonid Yegoshin authored
Add processor identifiers for single core and multi-core proAptiv processors. Signed-off-by:
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Leonid Yegoshin authored
For MIPS32R3 supported cores, the EHINV bit needs to be set when invalidating the TLB. This is necessary because the legacy software method of representing an invalid TLB entry using an unmapped address value is not guaranteed to work. Signed-off-by:
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Steven J. Hill authored
MIPS32R3 introduced a new set of Segmentation Control registers which increase the flexibility of the segmented-based memory scheme. Signed-off-by:
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Leonid Yegoshin authored
New Aptiv cores support the TLBINVF instruction for flushing the VTLB. Signed-off-by:
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Markos Chandras authored
The UNIQUE_ENTRYHI definition was duplicated whenever there was the need to flush the TLB entries. We move this common definition to a header file. Signed-off-by:
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Leonid Yegoshin authored
Signed-off-by:
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Markos Chandras authored
Add support for including VPE and TC ids in /proc/cpuinfo output as appropriate when MT/SMTC is enabled. Reviewed-by:
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Leonid Yegoshin authored
Commit 225ae5fd "MIPS: Malta: Fix interupt number of CBUS UART" fixed the IRQ number for the ttyS2 CBUS UART. However, this now conflicts with the GIC IPI1 interrupt in CMP platforms. The Malta interrupt code arbitrarily binds IPIs to INT2 and INT3 and since ttyS2 uses the INT2 IRQ line, closing the device disables the INT2 interrupt and this effectively disables the IPI1 interrupt as well. This patch is mainly a workaround until the Malta code is fixed properly. Signed-off-by:
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Leonid Yegoshin authored
The cacheer register is always implemented in the same way in the MIPS32r2 Imgtec cores so print the ES bit when an cache error occurs. Signed-off-by:
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Steven J. Hill authored
If GIC is present, then use it to send IPIs between the cores. Using GIC for IPIs is simpler and is usable for multicore systems compared to the existing way of doing IPIs where all VPEs had to be disabled for another VPE to access the Cause register in one of the TCs and enable all the VPEs back. Signed-off-by:
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Markos Chandras authored
According to Documentation/cpu-hotplug.txt, the cpu_present_mask should contain all the CPUs which are present in the system. Therefore, all the TCs currently present in the system should be marked as 'present' even if they will never be brought online. Signed-off-by:
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Markos Chandras authored
According to MIPS32 and MIPS64 PRA documents, a value of 7 in IL and DL fields is marked as "Reserved" so panic if the core uses this value in the config1 register. Also simplify the code a little bit. Signed-off-by:
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