- 26 Jun, 2024 27 commits
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Haibo Xu authored
Enable the dmi driver for riscv which would allow access the SMBIOS info through some userspace file(/sys/firmware/dmi/*). The change was based on that of arm64 and has been verified by dmidecode tool. Signed-off-by:
Haibo Xu <haibo1.xu@intel.com> Reviewed-by:
Ard Biesheuvel <ardb@kernel.org> Reviewed-by:
Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20240613065507.287577-1-haibo1.xu@intel.comSigned-off-by:
Palmer Dabbelt <palmer@rivosinc.com>
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Alexandre Ghiti authored
Like other architectures, a pte is accessible if it is present or if there is a pending tlb flush and the pte is protnone (which could be the case when a pte is downgraded to protnone before a flush tlb is executed). Signed-off-by:
Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20240128115953.25085-1-alexghiti@rivosinc.comSigned-off-by:
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Palmer Dabbelt authored
Clément Léger <cleger@rivosinc.com> says: Add support for (yet again) more RVA23U64 missing extensions. Add support for Zimop, Zcmop, Zca, Zcf, Zcd and Zcb extensions ISA string parsing, hwprobe and kvm support. Zce, Zcmt and Zcmp extensions have been left out since they target microcontrollers/embedded CPUs and are not needed by RVA23U64. Since Zc* extensions states that C implies Zca, Zcf (if F and RV32), Zcd (if D), this series modifies the way ISA string is parsed and now does it in two phases. First one parses the string and the second one validates it for the final ISA description. * b4-shazam-merge: KVM: riscv: selftests: Add Zcmop extension to get-reg-list test RISC-V: KVM: Allow Zcmop extension for Guest/VM riscv: hwprobe: export Zcmop ISA extension riscv: add ISA extension parsing for Zcmop dt-bindings: riscv: add Zcmop ISA extension description KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test RISC-V: KVM: Allow Zca, Zcf, Zcd and Zcb extensions for Guest/VM riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensions riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb riscv: add ISA extensions validation callback dt-bindings: riscv: add Zca, Zcf, Zcd and Zcb ISA extension description KVM: riscv: selftests: Add Zimop extension to get-reg-list test RISC-V: KVM: Allow Zimop extension for Guest/VM riscv: hwprobe: export Zimop ISA extension riscv: add ISA extension parsing for Zimop dt-bindings: riscv: add Zimop ISA extension description Link: https://lore.kernel.org/r/20240619113529.676940-1-cleger@rivosinc.comSigned-off-by:
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Clément Léger authored
The KVM RISC-V allows Zcmop extension for Guest/VM so add this extension to get-reg-list test. Signed-off-by:
Clément Léger <cleger@rivosinc.com> Reviewed-by:
Anup Patel <anup@brainfault.org> Acked-by:
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Clément Léger authored
Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zcmop extension for Guest/VM. Signed-off-by:
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Clément Léger authored
Export Zcmop ISA extension through hwprobe. Signed-off-by:
Evan Green <evan@rivosinc.com> Link: https://lore.kernel.org/r/20240619113529.676940-15-cleger@rivosinc.comSigned-off-by:
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Clément Léger authored
Add parsing for Zcmop ISA extension which was ratified in commit c732a4f39a4c ("Zcmop is ratified/1.0") of the riscv-isa-manual. Signed-off-by:Conor Dooley <conor.dooley@microchip.com> Reviewed-by:
Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20240619113529.676940-14-cleger@rivosinc.comSigned-off-by:
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Clément Léger authored
Add description for the Zcmop (Compressed May-Be-Operations) ISA extension which was ratified in commit c732a4f39a4c ("Zcmop is ratified/1.0") of the riscv-isa-manual. Signed-off-by: -
Clément Léger authored
The KVM RISC-V allows Zca, Zcf, Zcd and Zcb extensions for Guest/VM so add these extensions to get-reg-list test. Signed-off-by:
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Clément Léger authored
Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zca, Zcf, Zcd and Zcb extensions for Guest/VM. Signed-off-by:
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Clément Léger authored
Export Zca, Zcf, Zcd and Zcb ISA extension through hwprobe. Signed-off-by:
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Clément Léger authored
The Zc* standard extension for code reduction introduces new extensions. This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp are left out of this patch since they are targeting microcontrollers/ embedded CPUs instead of application processors. Signed-off-by:
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Clément Léger authored
Since a few extensions (Zicbom/Zicboz) already needs validation and future ones will need it as well (Zc*) add a validate() callback to struct riscv_isa_ext_data. This require to rework the way extensions are parsed and split it in two phases. First phase is isa string or isa extension list parsing and consists in enabling all the extensions in a temporary bitmask (source isa) without any validation. The second step "resolves" the final isa bitmap, handling potential missing dependencies. The mechanism is quite simple and simply validate each extension described in the source bitmap before enabling it in the resolved isa bitmap. validate() callbacks can return either 0 for success, -EPROBEDEFER if extension needs to be validated again at next loop. A previous ISA bitmap is kept to avoid looping multiple times if an extension dependencies are never satisfied until we reach a stable state. In order to avoid any potential infinite looping, allow looping a maximum of the number of extension we handle. Zicboz and Zicbom extensions are modified to use this validation mechanism. Signed-off-by:
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Clément Léger authored
Add description for Zca, Zcf, Zcd and Zcb extensions which are part the Zc* standard extensions for code size reduction. Additional validation rules are added since Zcb depends on Zca, Zcf, depends on Zca and F, Zcd depends on Zca and D and finally, Zcf can not be present on rv64. Signed-off-by:
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Clément Léger authored
The KVM RISC-V allows Zimop extension for Guest/VM so add this extension to get-reg-list test. Signed-off-by:
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Clément Léger authored
Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zimop extension for Guest/VM. Signed-off-by:
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Clément Léger authored
Export Zimop ISA extension through hwprobe. Signed-off-by:
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Clément Léger authored
Add parsing for Zimop ISA extension which was ratified in commit 58220614a5f of the riscv-isa-manual. Signed-off-by:
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Clément Léger authored
Add description for the Zimop (May-Be-Operations) ISA extension which was ratified in commit 58220614a5f of the riscv-isa-manual. Signed-off-by:
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Palmer Dabbelt authored
Samuel Holland <samuel.holland@sifive.com> says: Here are a few changes to minimize calls to stop_machine() and flush_icache_*() in the various text patching functions, as well as to simplify the code. * b4-shazam-merge: riscv: Remove extra variable in patch_text_nosync() riscv: Use offset_in_page() in text patching functions riscv: Pass patch_text() the length in bytes riscv: Simplify text patching loops riscv: kprobes: Use patch_text_nosync() for insn slots riscv: jump_label: Simplify assembly syntax riscv: jump_label: Batch icache maintenance Link: https://lore.kernel.org/r/20240327160520.791322-1-samuel.holland@sifive.comSigned-off-by:
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Samuel Holland authored
This cast is superfluous, and is incorrect anyway if compressed instructions may be present. Reviewed-by:
Björn Töpel <bjorn@rivosinc.com> Signed-off-by:
Samuel Holland <samuel.holland@sifive.com> Reviewed-by:
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Samuel Holland authored
This is a bit easier to parse than the equivalent bit manipulation. Reviewed-by:
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Samuel Holland authored
patch_text_nosync() already handles an arbitrary length of code, so this removes a superfluous loop and reduces the number of icache flushes. Reviewed-by:
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Samuel Holland authored
This reduces the number of variables and makes the code easier to parse. Signed-off-by:
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Samuel Holland authored
These instructions are not yet visible to the rest of the system, so there is no need to do the whole stop_machine() dance. Reviewed-by:
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Samuel Holland authored
The idiomatic way to write "jal zero" is "j". Reviewed-by:
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Samuel Holland authored
Switch to the batched version of the jump label update functions so instruction cache maintenance is deferred until the end of the update. Reviewed-by:
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- 24 Jun, 2024 3 commits
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Palmer Dabbelt authored
Kanak Shilledar <kanakshilledar@gmail.com> says: This series of patches converts the RISC-V CPU interrupt controller to the newer dt-schema binding. Patch 1: This patch is currently at v4 as it has been previously rolled out. Contains the bindings for the interrupt controller. Patch 2: This patch is currently at v4. Contains the reference to the above interrupt controller. Thus, making all the RISC-V interrupt controller bindings in a centralized place. These patches are interdependent. Fixed the patch address mismatch error by changing DCO to @gmail.com Kanak Shilledar (3): dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema dt-bindings: riscv: cpus: add ref to interrupt-controller dt-bindings: serial: vt8500-uart: convert to json-schema .../interrupt-controller/riscv,cpu-intc.txt | 52 ------------- .../interrupt-controller/riscv,cpu-intc.yaml | 73 +++++++++++++++++++ .../devicetree/bindings/riscv/cpus.yaml | 21 +----- .../bindings/serial/via,vt8500-uart.yaml | 46 ++++++++++++ .../bindings/serial/vt8500-uart.txt | 27 ------- 5 files changed, 120 insertions(+), 99 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml create mode 100644 Documentation/devicetree/bindings/serial/via,vt8500-uart.yaml delete mode 100644 Documentation/devicetree/bindings/serial/vt8500-uart.txt * b4-shazam-merge: dt-bindings: riscv: cpus: add ref to interrupt-controller dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema Link: https://lore.kernel.org/r/20240615021507.122035-1-kanakshilledar@gmail.comSigned-off-by:
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Kanak Shilledar authored
removed the redundant properties for interrupt-controller and provide reference to the riscv,cpu-intc.yaml which defines the interrupt-controller. making the properties for riscv interrupt-controller at a central place. Reviewed-by:
Kanak Shilledar <kanakshilledar@gmail.com> Link: https://lore.kernel.org/r/20240615021507.122035-3-kanakshilledar@gmail.comSigned-off-by:
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Kanak Shilledar authored
Convert the RISC-V Hart-Level Interrupt Controller (HLIC) to newer DT schema, Created DT schema based on the .txt file which had `compatible`, `#interrupt-cells` and `interrupt-controller` as required properties. Changes made with respect to original file: - Changed the example to just use interrupt-controller instead of using the whole cpu block - Changed the example compatible string. Reviewed-by:
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- 30 May, 2024 9 commits
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Palmer Dabbelt authored
Andy Chiu <andy.chiu@sifive.com> says: The series composes of two parts. The first part Specifically, patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how vlenb is observed by the system. Patch 2 fixes the issue by failing the boot process of a secondary core if vlenb mismatches. Here is the organization of the series: - Patch 1, 2 provide a fix for mismatching vlen problem [1]. The solution is to fail secondary cores if their vlenb is not the same as the boot core. - Patch 3 is a cleanup for introducing ZVE* Vector subextensions. It gives the obsolete ISA parser the ability to expand ISA extensions for sigle letter extensions. - Patch 4, 5, 6 introduce Zve32x, Zve32f, Zve64x, Zve64f, Zve64d for isa parsing and hwprobe, and document about it. - Patch 7 makes has_vector() check against ZVE32X instead of V, so most userspace Vector supports will be available for bare ZVE32X. - Patch 8 updates the prctl test so that it runs on ZVE32X. The series is tested on a QEMU and verified that booting, Vector programs context-switch, signal, ptrace, prctl interfaces works when we only report partial V from the ISA. * b4-shazam-lts: selftest: run vector prctl test for ZVE32X riscv: vector: adjust minimum Vector requirement to ZVE32X riscv: hwprobe: add zve Vector subextensions into hwprobe interface riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description riscv: cpufeature: call match_isa_ext() for single-letter extensions riscv: vector: add a comment when calling riscv_setup_vsize() riscv: smp: fail booting up smp if inconsistent vlen is detected [Palmer: reorder the first two patches so I can merge the fix, and rebase this on v6.10-rc1 so it's a little easier to manage.] Link: https://lore.kernel.org/r/20240510-zve-detection-v5-0-0711bdd26c12@sifive.comSigned-off-by:
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Andy Chiu authored
The minimal requirement for running Vector subextension on Linux is ZVE32X. So change the test accordingly to run prctl as long as it find it. Signed-off-by:
Andy Chiu <andy.chiu@sifive.com> Link: https://lore.kernel.org/r/20240510-zve-detection-v5-8-0711bdd26c12@sifive.comSigned-off-by:
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Andy Chiu authored
Make has_vector() to check for ZVE32X. Every in-kernel usage of V that requires a more complicate version of V must then call out explicitly. Also, change riscv_v_first_use_handler(), and boot code that calls riscv_v_setup_vsize() to accept ZVE32X. Most kernel/user interfaces requires minimum of ZVE32X. Thus, programs compiled and run with ZVE32X should be supported by the kernel on most aspects. This includes context-switch, signal, ptrace, prctl, and hwprobe. One exception is that ELF_HWCAP returns 'V' only if full V is supported on the platform. This means that the system without a full V must not rely on ELF_HWCAP to tell whether it is allowable to execute Vector without first invoking a prctl() check. Signed-off-by:
Joel Granados <j.granados@samsung.com> Link: https://lore.kernel.org/r/20240510-zve-detection-v5-7-0711bdd26c12@sifive.comSigned-off-by:
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Andy Chiu authored
The following Vector subextensions for "embedded" platforms are added into RISCV_HWPROBE_KEY_IMA_EXT_0: - ZVE32X - ZVE32F - ZVE64X - ZVE64F - ZVE64D Extensions ending with an X indicates that the platform doesn't have a vector FPU. Extensions ending with F/D mean that whether single (F) or double (D) precision vector operation is supported. The number 32 or 64 follows from ZVE tells the maximum element length. Signed-off-by:
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Andy Chiu authored
Multiple Vector subextensions are added. Also, the patch takes care of the dependencies of Vector subextensions by macro expansions. So, if some "embedded" platform only reports "zve64f" on the ISA string, the parser is able to expand it to zve32x zve32f zve64x and zve64f. Signed-off-by:
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Andy Chiu authored
Add description for Zve32x Zve32f Zve64x Zve64f Zve64d ISA extensions. Signed-off-by:
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Andy Chiu authored
Single-letter extensions may also imply multiple subextensions. For example, Vector extension implies zve64d, and zve64d implies zve64f. Extension parsing for "riscv,isa-extensions" has the ability to resolve the dependency by calling match_isa_ext(). This patch makes deprecated parser call the same function for single letter extensions. Signed-off-by:
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Andy Chiu authored
Currently we only support Vector for SMP platforms, that is, all SMP cores have the same vlenb. If we happen to detect a mismatching vlen, it is better to just fail bootting it up to prevent further race/scheduling issues. Also, move .Lsecondary_park forward and chage `tail smp_callin` into a regular call in the early assembly. So a core would be parked right after a return from smp_callin. Note that a successful smp_callin does not return. Fixes: 7017858e ("riscv: Introduce riscv_v_vsize to record size of Vector context") Reported-by:
Yunhui Cui <cuiyunhui@bytedance.com> Link: https://lore.kernel.org/r/20240510-zve-detection-v5-2-0711bdd26c12@sifive.comSigned-off-by:
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Andy Chiu authored
The function would fail when it detects the calling hart's vlen doesn't match the first one's. The boot hart is the first hart calling this function during riscv_fill_hwcap, so it is impossible to fail here. Add a comment about this behavior. Signed-off-by:
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- 26 May, 2024 1 commit
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Linus Torvalds authored
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