- 30 Mar, 2017 40 commits
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Felix Kuehling authored
Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Alex Deucher authored
The RB harvest registers are not necessary, the driver already exposes this info via the info ioctl. GB_BACKEND_MAP has been deprecated since SI and is not relevant to the RB mapping. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Required for SR-IOV and saves MMIO transactions. v2: drop cached RB harvest registers Reviewed-by:
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Alex Deucher authored
Match what we do for other asics. Reviewed-by:
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Alex Deucher authored
We check the mem config register to make sure it's been programmed by the vbios to determine if we need to post so we check for a non-0 value. However, when the asic comes out of reset, we may see all ones here, so check for that too. Reviewed-by:
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Andrey Grodzovsky authored
This used by DAL ISR logic for VBLANK handling. Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Monk Liu authored
1) Adapt to vulkan: Now use double SWITCH BUFFER to replace the 128 nops w/a, because when vulkan introduced, umd can insert 7 ~ 16 IBs per submit which makes 256 DW size cannot hold the whole DMAframe (if we still insert those 128 nops), CP team suggests use double SWITCH_BUFFERs, instead of tricky 128 NOPs w/a. 2) To fix the CE VM fault issue when MCBP introduced: Need one more COND_EXEC wrapping IB part (original one us for VM switch part). this change can fix vm fault issue caused by below scenario without this change: >CE passed original COND_EXEC (no MCBP issued this moment), proceed as normal. >DE catch up to this COND_EXEC, but this time MCBP issued, thus DE treats all following packages as NOP. The following VM switch packages now looks just as NOP to DE, so DE dosen't do VM flush at all. >Now CE proceeds to the first IBc, and triggers VM fault, because DE didn't do VM flush for this DMAframe. 3) change estimated alloc size for gfx9. with new DMAframe scheme, we need modify emit_frame_size for gfx9 4) No need to insert 128 nops after gfx8 vm flush anymore because there was double SWITCH_BUFFER append to vm flush, and for gfx7 we already use double SWITCH_BUFFER following after vm_flush so no change needed for it. 5) Change emit_frame_size for gfx8 v2: squash in BUG removal from Monk Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Acked-by:
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Monk Liu authored
those MC_VM registers won't be programed by VBIOS in VF so driver is responsible to programe them. Signed-off-by:
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Monk Liu authored
ring_write_multiple should use buf_mask instead of ptr_mask Signed-off-by:
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Monk Liu authored
for SRIOV we cannot use access register when in IRQ routine with regular KIQ method Signed-off-by:
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Monk Liu authored
no CG for SRIOV on SOC15 Signed-off-by:
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Monk Liu authored
no hw_fini for SRIOV, otherwise other VF will be affected no CG for SRIOV Signed-off-by:
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Monk Liu authored
must set minor_update.enable before write smaller value to wptr/doorbell, so for sriov we need set that register bit in hw_init period. this could fix the SDMA ring test fail after guest reboot Signed-off-by:
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Monk Liu authored
ring->buf_mask need be set prior to ring_clear_ring invoke and fix ring_clear_ring as well which should use buf_mask instead of ptr_mask Signed-off-by:
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Monk Liu authored
this must be invoked during early init Signed-off-by:
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Monk Liu authored
when MCBP supported, we will set pre_enb bit for those IBs with PREEMPT flag tagged Signed-off-by:
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Monk Liu authored
Preamble in linux doesn't mean it is CE PREAMBLE IB, instead it means this IB could be dropped if no ctx switch happens. Signed-off-by:
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Monk Liu authored
Apply the new IB during IB emit for SRIOV with MCBP v2: agd: use define instead of magic number Signed-off-by:
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Monk Liu authored
set bit 21 of IB.control filed to actually enable MCBP for SRIOV v2: add flag for preemption enable bit for soc15 and use this flag instead of hardcode. Signed-off-by:
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Monk Liu authored
when MCBP enabled for gfx8, the cond_exec must also be implemented, otherwise there will be odds to meet cross engine (ce and me) deadlock when world switch happens. Signed-off-by:
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Monk Liu authored
1,the check is only appliable for SRIOV GFX engine. 2,use chunk_ib instead of ib. Signed-off-by:
Ken Wang <Qingqing.wang@amd.com> Signed-off-by:
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Monk Liu authored
to prevent submit two or more IBs with PREEMPT flags. Signed-off-by:
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Monk Liu authored
should use chunk_ib instead of ib, otherwise the logic is incorrect. Signed-off-by:
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Nicolai Hähnle authored
Also, add the fence of the clear operations to the BO to ensure that the underlying memory can only be re-used after all PTEs pointing to it have been cleared. This avoids the following sequence of events that could be triggered by user space: 1. Submit a CS that accesses some BO _without_ adding that BO to the buffer list. 2. Free that BO. 3. Some other task re-uses the memory underlying the BO. 4. The CS is submitted to the hardware and accesses memory that is now already in use by somebody else. By clearing the page tables immediately in step 2, a GPU VM fault will be triggered in step 4 instead of wild memory accesses. v2: use amdgpu_bo_fence directly Signed-off-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Chunming Zhou authored
Signed-off-by:
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Chunming Zhou authored
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Chunming Zhou authored
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Chunming Zhou authored
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Chunming Zhou authored
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Christian König authored
Allocate and free page directories on demand. V2: a. clear entries allocation b. fix entries index calculation c. need alloc sub level even parent bo was allocated Signed-off-by: Christian König <christian.koenig@amd.com> (v1) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1) Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> (v2) Acked-by: Alex Deucher <alexander.deucher@amd.com> (v2) Signed-off-by: -
Christian König authored
Not the best solution, but good enough for now. Signed-off-by:
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Christian König authored
Update all levels of the page directory. V2: a. sub level pdes always are written to incorrect place. b. sub levels need to update regardless of parent updates. Signed-off-by: Christian König <christian.koenig@amd.com> (V1) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (V1) Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> (V2) Acked-by: Alex Deucher <alexander.deucher@amd.com> (V2) Signed-off-by: -
Christian König authored
Move all levels to the end after command submission. Signed-off-by:
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Christian König authored
All page directory levels should be in place after this. Signed-off-by:
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Christian König authored
Allows us to get the size for all levels as well. v2: agd: fix warning Signed-off-by:
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Christian König authored
No functional change, but the base for multi level page tables. Signed-off-by:
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Christian König authored
Needs to be filled with handling. Signed-off-by:
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Christian König authored
This way we save passing it through the different functions. Signed-off-by:
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Christian König authored
Decribes better what this is used for. Signed-off-by:
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Rex Zhu authored
for power readings. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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