- 27 Jul, 2020 40 commits
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Mauro Rossi authored
[Why] DCE6 has no FMT_TRUNCATE_MODE bit in FMT_BIT_DEPTH_CONTROL register DCE6 has no FMT_CLAMP_COMPONENT_{R,G,B} registers DCE6 has no FMT_SUBSAMPLING_{MODE,ORDER} bits in FMT_CONTROL register [How] Add DCE6 specific macros definitions for OPP registers and masks DCE6 OPP macros will avoid buiding errors when using DCE6 headers Add dce60_set_truncation() w/o FMT_TRUNCATE_MODE bit programming Add dce60_opp_set_clamping() w/o Format Clamp Component programming Add dce60_opp_program_fmt() w/o Format Subsampling bits programming Add dce60_opp_program_bit_depth_reduction() with dce60_set_truncation Use dce60_opp_program_fmt() in dce60_opp_funcs Use dce60_opp_program_bit_depth_reduction() in dce60_opp_funcs Add DCE6 specific dce60_opp_construct Reviewed-by:Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Mauro Rossi <issor.oruam@gmail.com> Signed-off-by:
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Mauro Rossi authored
[Why] DCE6 has DPG_PIPE_ARBITRATION_CONTROL3 register for Line Buffer watermark selection DCE6 has STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK mask for Stutter watermark selection DCE6 has NB_PSTATE_CHANGE_WATERMARK_MASK mask for North Bridge watermark selection DCE6 has no GRPH_MICRO_TILE_MODE mask DCE6 has no HW_ROTATION register [How] Add DCE6 specific macros definitions for MI registers and masks Add DCE6 specific registers to dce_mem_input_registers struct Add DCE6 specific masks to dce_mem_input_masks struct DCE6 MI macros/structs changes will avoid buiding errors when using DCE6 headers Add dce60_program_urgency_watermark() function Add dce60_program_nbp_watermark() function Add dce60_program_stutter_watermark() function Add dce60_mi_program_display_marks() function w/ new DCE6 watermark programming Add DCE6 specific tiling programming and modify DCE8 case Add dce60_program_size() fuction w/o Rotation processing Add dce60_mi_program_surface_config() fuction Use dce60_mi_program_display_marks() in dce60_mi_funcs Use dce60_mi_program_surface_config() in dce60_mi_funcs Add DCE6 specific dce60_mem_input_construct v2: remove unused variable (Alex) Reviewed-by:
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Mauro Rossi authored
[Why] DCE6 has no DP_DPHY_SCRAM_CNTL register [How] Add DCE6 specific macros definitions for LE registers DCE6 LE macros will avoid buiding errors when using DCE6 headers Add dce60_set_dp_phy_pattern_hbr2_compliance_cp2520_2() w/o Scramble Control programming Add dce60_set_dp_phy_pattern_passthrough_mode() w/o Scramble Control programming Add dce60_configure_encoder() w/o Scramble Control programming Add dce60_link_encoder_enable_dp_output() w/ dce60_configure_encoder Add dce60_link_encoder_enable_dp_mst_output() w/ dce60_configure_encoder Add dce60_link_encoder_dp_set_phy_pattern() w/ dce60_set_dp_phy_pattern_passthrough_mode Use dce60_link_encoder_enable_dp_output() in dce60_lnk_enc_funcs Use dce60_link_encoder_enable_dp_mst_output() in dce60_lnk_enc_funcs Use dce60_link_encoder_dp_set_phy_pattern() in dce60_lnk_enc_funcs Add DCE6 specific dce60_link_encoder_construct Reviewed-by:
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Mauro Rossi authored
[Why] DCE6 does not have CURSOR2_DEGAMMA_MODE bit in DEGAMMA_CONTROL register [How] Add DCE6 specific macros definitions for IPP masks DCE6 IPP macros will avoid buiding errors when using DCE6 headers Add dce60_ipp_set_degamma() function w/o Cursor2 Degamma programming Use dce60_ipp_set_degamma() in ipp_funcs dce60_ipp_funcs Add DCE6 specific dce60_ipp_construct Reviewed-by:
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Mauro Rossi authored
[Why] DCE6 has no BLND_CONTROL register for Blender HW programming DCE6 has no BLND_V_UPDATE_LOCK register for Pipe Locking [How] Add DCE6 specific macros definitions for HWSEQ registers and masks DCE6 HWSEQ macros will avoid buiding errors when using DCE6 headers Add dce60_pipe_control_lock() stub with no op Reviewed-by:
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Mauro Rossi authored
[Why] DCE6 has no SMU_INTERRUPT_CONTROL register, but it's used for DCN10 and later [How] Add DCE6 specific macros definitions for DMCU registers and masks DCE6 DMCU macros will avoid buiding errors when using DCE6 headers There is no other change needed in dce_dcmu Reviewed-by:
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Mauro Rossi authored
[Why] DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE register [How] Add DCE6 specific macros definitions for AUD masks DCE6 AUD macros will avoid buiding errors when using DCE6 headers Add dce60_aud_wall_dto_setup() w/o 512*Fs programming Use dce60_aud_wall_dto_setup() in dce60_funcs Add DCE specific dce60_audio_create Reviewed-by:
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Mauro Rossi authored
[Why] Issue in the Mouse cursor size in Linux Desktop Environments [How] In DCE6 dc->caps.max_cursor_size need to be set as 64 instead of 128 Reviewed-by:
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Mauro Rossi authored
(v1) Changelog [Why] After commit c69dd2d0 "drm/amd/display: Refactor clk_mgr functions" dc/clk_mgr requires these changes to add SI parts support Necessary to avoid hitting default: ASSERT(0); /* Unknown Asic */ that would cause kernel freeze [How] Add case statement for FAMILY_SI chipsets (v2) Changelog [Why] DCE6 has no DPREFCLK_CNTL register [How] Add DCE6 specific macros definitions for CLK registers and masks Add DCE6 specific dce60/dce60_clk_mgr.c for DCE6 customization Code style: reuse all the public functions in dce100/dce_clk_mgr.h header Code style: use dce60_* static functions as per other DCE implementations Add dce60_get_dp_ref_freq_khz() w/o using DPREFCLK_CNTL register Use dce60_get_dp_ref_freq_khz() function in dce60_funcs Add DCE6 specific dce60_clk_mgr_construct dc/clk_mgr/dce_clk_mgr.c: use dce60_clk_mgr_construct for FAMILY_SI chipsets Add Makefile rules for dce60_clk_mgr.o target conditional to CONFIG_DRM_AMD_DC_SI Reviewed-by:
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Mauro Rossi authored
[Why] amdgpu_dm.c requires changes for SI chipsets init and irq handlers registration [How] SI support: load_dmcu_fw(), amdgpu_dm_initialize_drm_device(), dm_early_init() Add DCE6 specific dce60_register_irq_handlers() function (v1) NOTE: As per Kaveri and older amdgpu.dc=1 kernel cmdline is required (v2) fix for bc011f9 ("drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence") remove CHIP_HAINAN support since it does not have physical DCE6 module (v3) fix vblank irq support for DCE6 using ad hoc dce60_register_irq_handlers() replicating for vblank irq the behavior of dce110_register_irq_handlers() as per commit b57de80a ("drm/amd/display: Register on VLBLANK ISR.") (v4) updated due to following kernel 5.2 commit: b2fddb13 ("drm/amd/display: Drop underlay plane support") Reviewed-by: -
Mauro Rossi authored
[Why] irq service requires changes for DCE6 support [How] (v1) DCE6 targets are added replicating existing DCE8 implementation. due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks, dce/dce_8_0_{d,sh_mask}.h used instead of dce/dce_6_0_{d,sh_mask}.h (v2) DCE6 headers used adding the necessary vblank irq registers (INT_MASK and VBLANK_STATUS) and vblank irq masks as implemented in amdgpu driver. Add vblank_irq_info_funcs_dce60 with .set and .ack as per commit b10d51f8 ("drm/amd/display: Add interrupt entries for VBLANK isr.") and use it in vblank_int_entry(reg_num) macro definition (v3) updated due to following kernel 5.3 commit: 4fc4dca8 ("drm/amd: drop use of drmp.h in os_types.h") (v4) updated due to following kernel 5.6 commit: d9e32672 ("drm/amd/display: cleanup of construct and destruct funcs") Reviewed-by: -
Mauro Rossi authored
[Why] hw_factory.c requires changes for DCE6 support [How] DCE6 targets added replicating and adapting existing DCE8 implementation. (v2) changes due to following commit: 91db9311 ("drm/amd/display: refactor gpio to allocate hw_container in constructor") Reviewed-by: -
Mauro Rossi authored
[Why] command_table_helper.c requires changes for DCE6 support [How] DCE6 targets added replicating and adapting the existing DCE8 implementation. Reviewed-by:
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Mauro Rossi authored
[Why] resource_parse_asic_id() and dc_create_resource_pool() are missing SI/DCE6 cases [How] SI/DCE6 cases support added using existing DCE8 implementation as a reference (v2) updated due to following kernel 5.2 commit: d9673c92 ("drm/amd/display: Pass init_data into DCN resource creation") Reviewed-by: -
Mauro Rossi authored
[Why] DCE6 chipsets have a lot in common with DCE8, let's start from this [How] DCE6 targets are added replicating existing DCE8 implementation. NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h initial build prototype due to missing DCE6 macros/registers/masks DCE6 specific macros/registers/masks will be added with later commits (v2b) removed dce_version cases in dc/dce/dce_clock_source.c and updated dce60 due to following kernel 5.0 commits: 24f7dd7e ("drm/amd/display: move pplib/smu notification to dccg block") 9566b675 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead") 4244381c ("drm/amd/display: clean up base dccg struct") 4c5e8b54 ("drm/amd/display: split dccg clock manager into asic folders") 84e7fc05 ("drm/amd/display: rename dccg to clk_mgr") 77f6916a ("drm/amd/display: Remove duplicate header") 9f7ddbea ("drm/amd/display: fix optimize_bandwidth func pointer for dce80") 4ece61a2 ("drm/amd/display: set clocks to 0 on suspend on dce80") (v3b) updated dce60 due to following kernel 5.1 commits: 380604e2 ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks") 32e61361 ("drm/amd/display: Fix 64-bit division for 32-bit builds") 1877ccf6 ("drm/amd/display: Change from aux_engine to dce_aux") c69dffab ("drm/amd/display: fix eDP fast bootup for pre-raven asic") (v4b) updated dce60 due to following kernel 5.2 commits: e5c41970 ("drm/amd/display: Add plane capabilities to dc_caps") 813d20dc ("drm/amd/display: Fix multi-thread writing to 1 state") ea36ad34 ("drm/amd/display: expand plane caps to include fp16 and scaling capability") afcd526b ("drm/amd/display: Add fast_validate parameter") (v5b) updated dce60 due to following kernel 5.3 commits: e7e10c46 ("drm/amd/display: stop external access to internal optc sync params") 78cc70b1 ("drm/amd/display: Engine-specific encoder allocation") dc88b4a6 ("drm/amd/display: make clk mgr soc specific") 4fc4dca8 ("drm/amd: drop use of drmp.h in os_types.h") (v6b) updated dce60 due to following kernel 5.4 commits: 54a9bcb0 ("drm/amd/display: Fix a typo - dce_aduio_mask --> dce_audio_mask") 9adc8050 ("drm/amd/display: make firmware info only load once during dc_bios create") (v7b) updated dce60 due to following kernel 5.5 commits: cabe144b ("drm/amd/display: memory leak") 8276dd87 ("drm/amd/display: update register field access mechanism") f6040a43 ("drm/amd/display: configurable aux timeout support") bf7f5ac3 ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x") (v8b) updated dce60 due to following kernel 5.6 commits: d9e32672 ("drm/amd/display: cleanup of construct and destruct funcs") f42ea55b ("drm/amd/display: add separate of private hwss functions") (v9b) updated dce60 due to following kernel 5.8 commits: bba8289 ("drm/amd/display: code clean up in dce80_hw_sequencer.c") 904fb6e0 ("drm/amd/display: move panel power seq to new panel struct") d4caa72e ("drm/amd/display: change from panel to panel cntl") (v10) Fix up PLL handling for DCE6: DCE6.0 supports 2 PLLs. DCE6.1 supports 3 PLLs. (Alex) Reviewed-by: -
Mauro Rossi authored
[Why] Asic info for SI parts need to be preliminarly added [How] Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL Tree path: ./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h Reviewed-by:
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Alex Deucher authored
To help with the DC port. v2: add missing masks, add additional registers v3: more updates v4: fix accidently dropped changes v5: add missing nb pstate mask v6: add vblank, vline masks v7: add SCL_HORZ_FILTER_INIT regs Signed-off-by: -
Dan Carpenter authored
These tables have _COUNT number of elements so the comparisons should be >= instead of > to prevent reading one element beyond the end of the array. Fixes: 8264ee69 ("drm/amd/powerplay: drop unused code") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Christophe JAILLET authored
The wrappers in include/linux/pci-dma-compat.h should go away. The patch has been generated with the coccinelle script below and has been hand modified to replace GFP_ with a correct flag. It has been compile tested. When memory is allocated in 'radeon_gart_table_ram_alloc()' GFP_KERNEL can be used because its callers already use this flag. Both 'r100_pci_gart_init()' (r100.c) and 'rs400_gart_init()' (rs400.c) call 'radeon_gart_init()'. This function uses 'vmalloc'. @@ @@ - PCI_DMA_BIDIRECTIONAL + DMA_BIDIRECTIONAL @@ @@ - PCI_DMA_TODEVICE + DMA_TO_DEVICE @@ @@ - PCI_DMA_FROMDEVICE + DMA_FROM_DEVICE @@ @@ - PCI_DMA_NONE + DMA_NONE @@ expression e1, e2, e3; @@ - pci_alloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3; @@ - pci_zalloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3, e4; @@ - pci_free_consistent(e1, e2, e3, e4) + dma_free_coherent(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_single(e1, e2, e3, e4) + dma_map_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_single(e1, e2, e3, e4) + dma_unmap_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4, e5; @@ - pci_map_page(e1, e2, e3, e4, e5) + dma_map_page(&e1->dev, e2, e3, e4, e5) @@ expression e1, e2, e3, e4; @@ - pci_unmap_page(e1, e2, e3, e4) + dma_unmap_page(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_sg(e1, e2, e3, e4) + dma_map_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_sg(e1, e2, e3, e4) + dma_unmap_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_cpu(e1, e2, e3, e4) + dma_sync_single_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_device(e1, e2, e3, e4) + dma_sync_single_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_cpu(e1, e2, e3, e4) + dma_sync_sg_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_device(e1, e2, e3, e4) + dma_sync_sg_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2; @@ - pci_dma_mapping_error(e1, e2) + dma_mapping_error(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_dma_mask(e1, e2) + dma_set_mask(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_consistent_dma_mask(e1, e2) + dma_set_coherent_mask(&e1->dev, e2) Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Christophe JAILLET authored
Avoid a memset after a call to 'dma_alloc_coherent()'. This is useless since commit 518a2f19 ("dma-mapping: zero memory returned from dma_alloc_*") Reviewed-by:
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Bhawanpreet Lakha authored
Use DCN21 functions instead of DCE110 Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
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Bhawanpreet Lakha authored
[Why] Currently navy_flounder is using sienna_cichlid_dmcub.bin. [How] Create a seperate define so navy_flounder will use its own firmware. Signed-off-by:
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Martin Tsai authored
[Why] Some monitors could suffer symbol unlock but cannot send HPD IRQ to notic source device to handle link loss. This makes monitor stuck in abnormal status and causes black screen. [How] According to the suggestion from scalar vendor, to check lane status again after link training done. That can improve the comaptibility from current production monitors. Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Eryk Brol <eryk.brol@amd.com> Signed-off-by:
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Alvin Lee authored
[Why] In dcn3_update_clocks there are situations where dppclk is not lowered (i.e. stays the same), but DTO still needs to be increased before we program pipe frontend (i.e. in prepare_bandwidth). If we don't program the new DTO value before we program the pipe, we will underflow as soon as the pipe lock is released until the next call to dcn3_update_clocks where the DTO is updated. [How] Remove dppclk check before programming new DTO value. Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Eryk Brol authored
[why] Fix naming and return bits rather than bytes per pixel for naming consistency. Because registers return Bytes per pixel, but DSC Config structure is expecting bits per pixel as input. So when returning the value convert from bytes into bits. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Eryk Brol authored
[Why] Struct dcn_dsc_state is used for reading current state and parameters of DSC on a pipe, the target rate parameter uses bytes per pixel even though its reading BITS_PER_PIXEL register. [How] Changing it to Bits Per Pixel for consistency. Signed-off-by:
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Dmytro Laktyushkin authored
[Why] This change replaces older looping code in favor of these functions. [How] There are built in functions for extracting global sync params during mode validation now. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Kevin Wang authored
1. allow asic to handle sensor type by itself. 2. if not, use smu common sensor to handle it. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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John Clements authored
added support for umc 8.7 error reporting and query Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Likun Gao authored
Update sienna_cichlid driver if header and related files. Support new smu metrics for pre & postDS frequency. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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John Clements authored
the change introduces IP headers for unified memory controller (umc) Reviewed-by:
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Evan Quan authored
The current outputs of amdgpu_pm_info debugfs come with clock gating status and followed by current clock/power information. However the clock gating status retrieving may pull GFX out of CG status. That will make the succeeding clock/power information retrieving inaccurate. To overcome this and be with minimum impact, the outputs are updated to show current clock/power information first. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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James Zhu authored
This reverts commit 058c07201ec7d373fc6a0a570b38a8a9d62c29fb. Chip NAVY_FLOUNDER uses vcn3.0, but it has only one VCN instance. Signed-off-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Jay Cornwall authored
s_barrier triggers a debug exception when issued with PRIV=1, DEBUG_EN=1. This causes spurious notifications to rocm-gdb. Clear MODE before issuing s_barrier and restore MODE afterwards in the context restore handler. Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Tested-by:
Laurent Morichetti <laurent.morichetti@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Changfeng authored
Take back patch:drop unnecessary message support check Because the gpu reset fail problem on renoir can be fixed by: drm/amd/powerplay: skip invalid msg when smu set mp1 state It needs to remove SWSMU_CODE_LAYER_L1 in smu_cmn.h to guard a clear code layer. Signed-off-by:
changfeng <Changfeng.Zhu@amd.com> Reviewed-by:
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Mukul Joshi authored
Add support for reporting thermal throttling events through SMI. Also, add a counter to count the number of throttling interrupts observed and report the count in the SMI event message. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
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Dennis Li authored
when GPU hang, driver has multi-paths to enter amdgpu_device_gpu_recover, the atomic adev->in_gpu_reset and hive->in_reset are used to avoid re-entering GPU recovery. During GPU reset and resume, it is unsafe that other threads access GPU, which maybe cause GPU reset failed. Therefore the new rw_semaphore adev->reset_sem is introduced, which protect GPU from being accessed by external threads during recovery. v2: 1. add rwlock for some ioctls, debugfs and file-close function. 2. change to use dqm->is_resetting and dqm_lock for protection in kfd driver. 3. remove try_lock and change adev->in_gpu_reset as atomic, to avoid re-enter GPU recovery for the same GPU hang. v3: 1. change back to use adev->reset_sem to protect kfd callback functions, because dqm_lock couldn't protect all codes, for example: free_mqd must be called outside of dqm_lock; [ 1230.176199] Hardware name: Supermicro SYS-7049GP-TRT/X11DPG-QT, BIOS 3.1 05/23/2019 [ 1230.177221] Call Trace: [ 1230.178249] dump_stack+0x98/0xd5 [ 1230.179443] amdgpu_virt_kiq_reg_write_reg_wait+0x181/0x190 [amdgpu] [ 1230.180673] gmc_v9_0_flush_gpu_tlb+0xcc/0x310 [amdgpu] [ 1230.181882] amdgpu_gart_unbind+0xa9/0xe0 [amdgpu] [ 1230.183098] amdgpu_ttm_backend_unbind+0x46/0x180 [amdgpu] [ 1230.184239] ? ttm_bo_put+0x171/0x5f0 [ttm] [ 1230.185394] ttm_tt_unbind+0x21/0x40 [ttm] [ 1230.186558] ttm_tt_destroy.part.12+0x12/0x60 [ttm] [ 1230.187707] ttm_tt_destroy+0x13/0x20 [ttm] [ 1230.188832] ttm_bo_cleanup_memtype_use+0x36/0x80 [ttm] [ 1230.189979] ttm_bo_put+0x1be/0x5f0 [ttm] [ 1230.191230] amdgpu_bo_unref+0x1e/0x30 [amdgpu] [ 1230.192522] amdgpu_amdkfd_free_gtt_mem+0xaf/0x140 [amdgpu] [ 1230.193833] free_mqd+0x25/0x40 [amdgpu] [ 1230.195143] destroy_queue_cpsch+0x1a7/0x270 [amdgpu] [ 1230.196475] pqm_destroy_queue+0x105/0x260 [amdgpu] [ 1230.197819] kfd_ioctl_destroy_queue+0x37/0x70 [amdgpu] [ 1230.199154] kfd_ioctl+0x277/0x500 [amdgpu] [ 1230.200458] ? kfd_ioctl_get_clock_counters+0x60/0x60 [amdgpu] [ 1230.201656] ? tomoyo_file_ioctl+0x19/0x20 [ 1230.202831] ksys_ioctl+0x98/0xb0 [ 1230.204004] __x64_sys_ioctl+0x1a/0x20 [ 1230.205174] do_syscall_64+0x5f/0x250 [ 1230.206339] entry_SYSCALL_64_after_hwframe+0x49/0xbe 2. remove try_lock and introduce atomic hive->in_reset, to avoid re-enter GPU recovery. v4: 1. remove an unnecessary whitespace change in kfd_chardev.c 2. remove comment codes in amdgpu_device.c 3. add more detailed comment in commit message 4. define a wrap function amdgpu_in_reset v5: 1. Fix some style issues. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by:
Lijo Lazar <Lijo.Lazar@amd.com> Suggested-by:
Luben Tukov <luben.tuikov@amd.com> Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Signed-off-by:
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Boyuan Zhang authored
Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Colin Ian King authored
The variable result is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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James Zhu authored
vcn ip block is already selected based on ASIC type during set_ip_blocks. Signed-off-by:
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