- 01 Oct, 2015 7 commits
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Victorien Vedrine authored
On drivers/clk/mxs/clk-frac.c, the function clk_frac_round_rate returned a bad result. The division before multiplication computes a wrong value ; the calculation is inverted to fix the problem. The second issue is that the exact rate have decimals and they are truncate. The consequence is that the function clk_frac_set_rate (which use the result of clk_frac_round_rate) computes a wrong value for the register (the rate generated can be closer to the desired rate). The correction is : if there is decimal to the result, it is rounded to the next larger integer. On drivers/clk/mxs/clk-frac.c, the function clk_frac_recalc_rate returned a bad result. The multiplication is made before the division to compute a correct value. Signed-off-by:
Victorien Vedrine <victorien.vedrine@ophrys.net> Acked-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Andrzej Hajda authored
The function can return negative value. The problem has been detected using proposed semantic patch scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2046107Signed-off-by:
Andrzej Hajda <a.hajda@samsung.com> Signed-off-by:
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Heiko Stübner authored
Separate the update of pll registers from the actual set_rate function so that the init callback does not need to access clk-API functions. As we now have separated the getting and setting of the pll parameters we can also directly use these new functions in other places too. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
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Nicolas Ferre authored
Add a new type of clocks that can be provided to a peripheral. In addition to the peripheral clock, this new clock that can use several input clocks as parents can generate divided rates. This would allow a peripheral to have finer grained clocks for generating a baud rate, clocking an asynchronous part or having more options in frequency. Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> [sboyd@codeaurora.org: Transition to new clk_hw provider APIs] Signed-off-by:
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Nicolas Ferre authored
Add support for the new sama5d2 SoC and adapt capabilities. Signed-off-by:
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Nicolas Ferre authored
As some more information is added to the PCR register, we'd better use a copy of its content and modify just the peripheral-related bits. Implement a read-modify-write for the enable() and disable() callbacks. Signed-off-by:
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Nicolas Ferre authored
Add _MASK and _OFFSET values and cleanup register fields layout. Signed-off-by:
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- 29 Sep, 2015 2 commits
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Guo Zeng authored
Power management on of NoC(Notwork On Chip) requires that disconnect and reconnect routine should been done during clk disable/enable. also there are different types of clocks, For NoC Macro clocks, write idle_bit and wait for hardward ACK; For Socket clocks, write idle_bit; For others, do nothing. Signed-off-by:
Guo Zeng <Guo.Zeng@csr.com> Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
Michael Turquette <mturquette@baylibre.com>
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Guo Zeng authored
re-order the codes more reasonable by moving variable-definition together. Signed-off-by:
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- 22 Sep, 2015 2 commits
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Stephen Boyd authored
* clk-fixes: clk: samsung: fix cpu clock's flags checking
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Bartlomiej Zolnierkiewicz authored
CLK_CPU_HAS_DIV1 and CLK_CPU_NEEDS_DEBUG_ALT_DIV masks were incorrectly used as a bit numbers. Fix it. Tested on Exynos4210 based Origen board and on Exynos5250 based Arndale board. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Fixes: ddeac8d9 ("clk: samsung: add infrastructure to register cpu clocks") Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by:
Javier Martinez Canillas <javier@dowhile0.org> Acked-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by:
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- 17 Sep, 2015 7 commits
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Georgi Djakov authored
Add support for the msm8916 audio clocks. This includes core bus, low-power audio and codec clocks. They are required for audio playback. Signed-off-by:
Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by:
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Georgi Djakov authored
Add support for the msm8916 BIMC (Bus Integrated Memory Controller) clocks that are needed for GPU. Signed-off-by:
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Georgi Djakov authored
Some root clock generators may have child branches that are controlled by different CPUs. These RCGs require some special operations: - some enable bits have to be toggled when we set the rate; - if RCG is disabled we only cache the rate and set it later when enabled; - when the RCG is disabled, the mux is set to the safe source; Signed-off-by:
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Georgi Djakov authored
Add support for the msm8916 TCU (Translation Control Unit) clocks that are needed for IOMMU. Signed-off-by:
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Stephen Boyd authored
* clk-fixes: drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x clk: check for invalid parent index of orphans in __clk_init()
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Gabriel Fernandez authored
Use a generic name for this kind of PLL Correction in dts files are already done here: commit 5eb26c60 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x") Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by:
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Javier Martinez Canillas authored
There are cleary typo errors so can be removed. Signed-off-by:
Javier Martinez Canillas <javier@osg.samsung.com> Acked-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
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- 16 Sep, 2015 21 commits
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Mans Rullgard authored
If a mux clock is initialised (by hardware or firmware) with an invalid parent, its ->get_parent() can return an out of range index. For example, the generic mux clock attempts to return -EINVAL, which due to the u8 return type ends up a rather large number. Using this index with the parent_names[] array results in an invalid pointer and (usually) a crash in the following strcmp(). This patch adds a check for the parent index being in range, ignoring clocks reporting invalid values. Signed-off-by:
Mans Rullgard <mans@mansr.com> Tested-by:
Rhyland Klein <rklein@nvidia.com> Signed-off-by:
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Stephane Viau authored
Add the GDSC instances that exist as part of apq8084 MMCC block. Signed-off-by:
Stephane Viau <sviau@codeaurora.org> Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by:
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Rajendra Nayak authored
Add the GDSC instances that exist as part of apq8084 GCC block Signed-off-by:
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Stephen Boyd authored
Add the GDSC instances that exist as part of msm8974 MMCC block Signed-off-by:
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Stephen Boyd authored
There's just one GDSC as part of the msm8974 GCC block. Signed-off-by:
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Rajendra Nayak authored
Add all data for the GDSCs which are part of msm8916 GCC block. Signed-off-by:
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Rajendra Nayak authored
Certain devices can have GDSCs' which support ON as the only state. They can't be power collapsed to either hit RET or OFF. The clients drivers for these GDSCs' however would expect the state of the core to be reset following a GDSC disable and re-enable. To do this assert/deassert reset lines every time the client driver would request the GDSC to be powered on/off instead. Signed-off-by:
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Rajendra Nayak authored
Along with the GDSC power switch, there is additional control to either retain all memory (core and peripheral) within a given powerdomain or to turn them off while the GDSC is powered down. Add support for these by modelling a RET state where all memory is retained and an OFF state where all memory gets turned off. The controls provided are granular enough to be able to support various differnt levels of RET states, like a 'shallow RET' with all memory retained and a 'deep RET' with some memory retained while some others are lost. The current patch does not support this and considers just one RET state where all memory is retained. Futher work, if needed can support multiple different levels of RET state. Signed-off-by:
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Rajendra Nayak authored
The common clk probe registers a clk provider and a reset controller. Update it to register a genpd provider using the gdsc data provided by each platform. Signed-off-by:
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Stephen Boyd authored
GDSCs (Global Distributed Switch Controllers) are responsible for safely collapsing and restoring power to peripherals in the SoC. These are best modelled as power domains using genpd and given the registers are scattered throughout the clock controller register space, its best to have the support added through the clock driver. Signed-off-by:
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Brian Norris authored
On 32-bit architectures, 'unsigned long' (the type used to hold clock rates, in Hz) is often only 32 bits wide. DIV_ROUND_UP() (as used in, e.g., commit b11d282d "clk: divider: fix rate calculation for fractional rates") can yield an integer overflow on clock rates that are not (by themselves) too large to fit in 32 bits, because it performs addition before the division. See for example: DIV_ROUND_UP(3000000000, 1500000000) = (3.0G + 1.5G - 1) / 1.5G = OVERFLOW / 1.5G This patch fixes such cases by always promoting the dividend to 64-bits (unsigned long long) before doing the division. While this patch does not resolve the issue with large clock rates across the common clock framework nor address the problems with doing full 64-bit arithmetic on a 32-bit architecture, it does fix some issues seen when using clock dividers on a 3GHz reference clock to produce a 1.5GHz CPU clock for an ARMv7 Brahma B15 SoC. Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Reference: http://lkml.kernel.org/g/20150413201433.GQ32500@ld-irv-0074Signed-off-by:
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Luis de Bethencourt authored
This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by:
Luis de Bethencourt <luis@debethencourt.com> Signed-off-by:
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Luis de Bethencourt authored
This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by:
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Luis de Bethencourt authored
This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by:
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Luis de Bethencourt authored
This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by:
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Luis de Bethencourt authored
This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by:
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Alexandre Belloni authored
In the error path of at91_clk_register_system(), sys->irq is freed unconditionally but it may not exist or be request at all. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
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Alexandre Belloni authored
at91_pmc_read is a workaround to allow external drivers to acces some registers of the PMC. There is no need for it in clk-utmi.c as we aready have a pointer to the struct at91_pmc. Signed-off-by:
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Stephen Boyd authored
Sometimes the display driver may want to change the parent PLL of the display clocks (byte and pixel clocks) depending on the use-case. Currently the parent is fixed by means of having a frequency table with one entry that chooses a particular parent. Remove this restriction and use the parent the clock is configured for in the hardware during clk_set_rate(). This requires consumers to rely on the default parent or to configure the parent with clk_set_parent()/assigned-clock-parents on the clocks before calling clk_set_rate(). Tested-by:
Archit Taneja <architt@codeaurora.org> Cc: Hai Li <hali@codeaurora.org> Signed-off-by:
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Stephen Boyd authored
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Thierry Reding authored
The OPP list needs to be protected against concurrent accesses. Using simple RCU read locks does the trick and gets rid of the following lockdep warning: =============================== [ INFO: suspicious RCU usage. ] 4.2.0-next-20150908 #1 Not tainted ------------------------------- drivers/base/power/opp.c:460 Missing rcu_read_lock() or dev_opp_list_lock protection! other info that might help us debug this: rcu_scheduler_active = 1, debug_locks = 0 4 locks held by kworker/u8:0/6: #0: ("%s""deferwq"){++++.+}, at: [<c0040d8c>] process_one_work+0x118/0x4bc #1: (deferred_probe_work){+.+.+.}, at: [<c0040d8c>] process_one_work+0x118/0x4bc #2: (&dev->mutex){......}, at: [<c03b8194>] __device_attach+0x20/0x118 #3: (prepare_lock){+.+...}, at: [<c054bc08>] clk_prepare_lock+0x10/0xf8 stack backtrace: CPU: 2 PID: 6 Comm: kworker/u8:0 Not tainted 4.2.0-next-20150908 #1 Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) Workqueue: deferwq deferred_probe_work_func [<c001802c>] (unwind_backtrace) from [<c00135a4>] (show_stack+0x10/0x14) [<c00135a4>] (show_stack) from [<c02a8418>] (dump_stack+0x94/0xd4) [<c02a8418>] (dump_stack) from [<c03c6f6c>] (dev_pm_opp_find_freq_ceil+0x108/0x114) [<c03c6f6c>] (dev_pm_opp_find_freq_ceil) from [<c0551a3c>] (dfll_calculate_rate_request+0xb8/0x170) [<c0551a3c>] (dfll_calculate_rate_request) from [<c0551b10>] (dfll_clk_round_rate+0x1c/0x2c) [<c0551b10>] (dfll_clk_round_rate) from [<c054de2c>] (clk_calc_new_rates+0x1b8/0x228) [<c054de2c>] (clk_calc_new_rates) from [<c054e44c>] (clk_core_set_rate_nolock+0x44/0xac) [<c054e44c>] (clk_core_set_rate_nolock) from [<c054e4d8>] (clk_set_rate+0x24/0x34) [<c054e4d8>] (clk_set_rate) from [<c0512460>] (tegra124_cpufreq_probe+0x120/0x230) [<c0512460>] (tegra124_cpufreq_probe) from [<c03b9cbc>] (platform_drv_probe+0x44/0xac) [<c03b9cbc>] (platform_drv_probe) from [<c03b84c8>] (driver_probe_device+0x218/0x304) [<c03b84c8>] (driver_probe_device) from [<c03b69b0>] (bus_for_each_drv+0x60/0x94) [<c03b69b0>] (bus_for_each_drv) from [<c03b8228>] (__device_attach+0xb4/0x118) ata1: SATA link down (SStatus 0 SControl 300) [<c03b8228>] (__device_attach) from [<c03b77c8>] (bus_probe_device+0x88/0x90) [<c03b77c8>] (bus_probe_device) from [<c03b7be8>] (deferred_probe_work_func+0x58/0x8c) [<c03b7be8>] (deferred_probe_work_func) from [<c0040dfc>] (process_one_work+0x188/0x4bc) [<c0040dfc>] (process_one_work) from [<c004117c>] (worker_thread+0x4c/0x4f4) [<c004117c>] (worker_thread) from [<c0047230>] (kthread+0xe4/0xf8) [<c0047230>] (kthread) from [<c000f7d0>] (ret_from_fork+0x14/0x24) Signed-off-by:Thierry Reding <treding@nvidia.com> Fixes: c4fe70ad ("clk: tegra: Add closed loop support for the DFLL") [vince.h@nvidia.com: Unlock rcu on error path] Signed-off-by:
Vince Hsu <vince.h@nvidia.com> [sboyd@codeaurora.org: Dropped second hunk that nested the rcu read lock unnecessarily] Signed-off-by:
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- 14 Sep, 2015 1 commit
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Heiko Stübner authored
Again a result of the gpio-clock-liberation the rk3368 needs the pclk_pd_pmu marked as critical, to boot successfully. Reported-by:
Mark Rutland <mark.rutland@arm.com> Signed-off-by:
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