1. 28 Dec, 2007 2 commits
    • Olof Johansson's avatar
      [POWERPC] pasemi: Distribute interrupts evenly across cpus · d87bf3be
      Olof Johansson authored
      By default the OpenPIC on PWRficient will bias to one core (since that
      will improve changes of the other core being able to stay idle/powered
      down). However, this conflicts with most irq load balancing schemes,
      since setting an interrupt to be delivered to either core doesn't really
      result in the load being shared. It also doesn't work well with the
      soft irq disable feature of PPC, since EE will stay on until the first
      interrupt is taken while soft disabled.
      
      Set the gconf0 config bit that enables even distribution of interrupts
      among the two cores.
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      d87bf3be
    • Olof Johansson's avatar
      [POWERPC] pasemi: Implement NMI support · f365355e
      Olof Johansson authored
      Some PWRficient-based boards have a NMI button that's wired up to a GPIO
      as interrupt source. By configuring the openpic accordingly, these get
      delivered as a machine check with high priority, instead of as an external
      interrupt.
      
      The device tree contains a property "nmi-source" in the openpic node
      for these systems, and it's the (hwirq) source for the input.
      
      Also, for these interrupts, the IACK is read from another register than
      the regular (MCACK instead), but they are EOI'd as usual. So implement
      said function for the mpic driver.
      
      Finally, move a couple of external function defines to include/ instead
      of local under sysdev. Being able to mask/unmask and eoi directly saves
      us from setting up a dummy irq handler that will never be called.
      Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
      f365355e
  2. 21 Dec, 2007 34 commits
  3. 20 Dec, 2007 4 commits