- 10 Feb, 2017 27 commits
-
-
Wei Yongjun authored
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Cédric Le Goater authored
This can be used to easily identify a specific chip on a system with multiple chips. Signed-off-by:
Cédric Le Goater <clg@kaod.org> Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Cédric Le Goater authored
This can be used to easily identify a specific chip on a system with multiple chips. Suggested-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
Cédric Le Goater <clg@kaod.org> Reviewed-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
git://github.com/spi-nor/linuxBrian Norris authored
From Cyrille: """ This pull request contains the following notable changes: - add support to the 4-byte address instruction set. - add support to new memory parts. - add support to S3AN memories. - add support to the Intel SPI controller. - add support to the Aspeed AST2400 and AST2550 controllers. - fix max SPI transfer and message sizes in m25p80_read(). - fix the Candence QSPI driver. - fix the Freescale QSPI driver. """
-
Brian Norris authored
physmap_of sort of depends on the gemini and versatile modules (when they're enabled), but this isn't expressed in Kconfig. Let's just merge the modules all together, when enabled. Then we can avoid exporting a few symbols, and the versatile and gemini code can now be modular again (the below commit accidentally made them built-in only). Resolves errors like this: ERROR: "of_flash_probe_versatile" [drivers/mtd/maps/physmap_of.ko] undefined! ERROR: "of_flash_probe_gemini" [drivers/mtd/maps/physmap_of.ko] undefined! Fixes: 56ff337e ("mtd: physmap_of: add a hook for Gemini flash probing") Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org>
-
Colin Ian King authored
Checking for ret < 0 is redundant because a previous check on ret being non-zero already handles the ret < 0 case. Remove the redundant code. Found by CoverityScan, CID#1398863, CID#1398864 Signed-off-by:
Colin Ian King <colin.king@canonical.com> Reviewed-by:
Richard Weinberger <richard@nod.at> Acked-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Guochun Mao authored
Add "mediatek,mt2701-nor" for nor flash node's compatible. Signed-off-by:
Guochun Mao <guochun.mao@mediatek.com> Acked-by:
John Crispin <john@phrozen.org> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Yunhui Cui authored
There are some read modes for flash, such as NORMAL, FAST, QUAD, DDR QUAD. These modes will use the identical lut table base So rename SEQID_QUAD_READ to SEQID_READ. Signed-off-by:
Yunhui Cui <B56489@freescale.com> Signed-off-by:
Yunhui Cui <yunhui.cui@nxp.com> Acked-by:
Han xu <han.xu@nxp.com> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Yunhui Cui authored
We can get the read/write/erase opcode from the spi nor framework directly. This patch uses the information stored in the SPI-NOR to remove the hardcode in the fsl_qspi_init_lut(). Signed-off-by:
Yunhui Cui <B56489@freescale.com> Signed-off-by:
Yunhui Cui <yunhui.cui@nxp.com> Acked-by:
Han xu <han.xu@nxp.com> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Kamal Dasu authored
Add GigaDevice GD25Q16 (16M-bit) to supported list. Signed-off-by:
Kamal Dasu <kdasu.kdev@gmail.com> Acked-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Ricardo Ribalda authored
The page calculation under spi_nor_s3an_addr_convert() was wrong. On Default Address Mode we need to perform a divide by page_size. Signed-off-by:
Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Cédric Le Goater authored
The first argument of ioread32_rep() and ioread8_rep is not const. Change aspeed_smc_read_from_ahb() prototype to fix compile warning : drivers/mtd/spi-nor/aspeed-smc.c: In function 'aspeed_smc_read_from_ahb': drivers/mtd/spi-nor/aspeed-smc.c:212:16: warning: passing argument 1 of 'ioread32_rep' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] ioread32_rep(src, buf, len >> 2); Signed-off-by:
Cédric Le Goater <clg@kaod.org> Reviewed-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Uwe Kleine-König authored
The MR25 family doesn't support JEDEC, so they need explicit mentioning in the list of supported spi IDs. This makes it possible to add these using for example: compatible = "everspin,mr25h40"; There was already an entry for mr25h256. Move that one out of the "keep for compatibility" section and put in a new group for Everspin MRAMs. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfdCyrille Pitchen authored
From Lee Jones: """ Immutable branch between MFD and MTD due for the v4.11 merge window """
-
Victor Shyba authored
This chip has write protection enabled on power-up, so this flag is necessary to support write operations. Signed-off-by:
Victor Shyba <victor1984@riseup.net> Acked-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Cyrille Pitchen authored
This patch provides an alternative mean to support memory above 16MiB (128Mib) by replacing 3byte address op codes by their associated 4byte address versions. Using the dedicated 4byte address op codes doesn't change the internal state of the SPI NOR memory as opposed to using other means such as updating a Base Address Register (BAR) and sending command to enter/leave the 4byte mode. Hence when a CPU reset occurs, early bootloaders don't need to be aware of BAR value or 4byte mode being enabled: they can still access the first 16MiB of the SPI NOR memory using the regular 3byte address op codes. Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com> Tested-by:
Vignesh R <vigneshr@ti.com> Acked-by:
Marek Vasut <marek.vasut@gmail.com>
-
Cyrille Pitchen authored
This patch renames the SPINOR_OP_* macros of the 4-byte address instruction set so the new names all share a common pattern: the 4-byte address name is built from the 3-byte address name appending the "_4B" suffix. The patch also introduces new op codes to support other SPI protocols such as SPI 1-4-4 and SPI 1-2-2. This is a transitional patch and will help a later patch of spi-nor.c to automate the translation from the 3-byte address op codes into their 4-byte address version. Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by:
Mark Brown <broonie@kernel.org> Acked-by:
Marek Vasut <marek.vasut@gmail.com>
-
Heiner Kallweit authored
Consider a message size limit when calculating the maximum amount of data that can be read. The message size limit has been introduced with 4.9, so cc it to stable. Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Cédric Le Goater authored
Signed-off-by:
Cédric Le Goater <clg@kaod.org> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Cédric Le Goater authored
This driver adds mtd support for the Aspeed AST2400 SoC static memory controllers: * New Static Memory Controller (referred as FMC) . BMC firmware . AST2500 compatible register set . 5 chip select pins (CE0 ∼ CE4) . supports NOR flash, NAND flash and SPI flash memory. * SPI Flash Controller (SPI) . host Firmware . slightly different register set, between AST2500 and the legacy controller . supports SPI flash memory . 1 chip select pin (CE0) The legacy static memory controller (referred as SMC) is not supported, as well as types other than SPI. Signed-off-by:
Cédric Le Goater <clg@kaod.org> Reviewed-by:
Joel Stanley <joel@jms.id.au> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Cédric Le Goater authored
This driver adds mtd support for the Aspeed AST2500 SoC static memory controllers : * Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0-CE1) . CE2 can be of NOR type flash but this is not supported by the driver * SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . supports SPI type flash memory Each controller has a memory range on which it maps its flash module slaves. Each slave is assigned a memory window for its mapping that can be changed at bootime with the Segment Address Register. Each SPI flash slave can then be accessed in two modes: Command and User. When in User mode, accesses to the memory segment of the slaves are translated in SPI transfers. When in Command mode, the HW generates the SPI commands automatically and the memory segment is accessed as if doing a MMIO. Currently, only the User mode is supported. Command mode needs a little more work to check that the memory window on the AHB bus fits the module size. Based on previous work from Milton D. Miller II <miltonm@us.ibm.com> Signed-off-by:
Cédric Le Goater <clg@kaod.org> Reviewed-by:
Joel Stanley <joel@jms.id.au> Reviewed-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Cyrille Pitchen authored
This patch removes the WARN_ONCE() test in spi_nor_write(). This macro triggers the display of a warning message almost every time we use a UBI file-system because a write operation is performed at offset 64, which is in the middle of the SPI NOR memory page. This is a valid operation for ubifs. Hence this warning is pretty annoying and useless so we just remove it. Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com> Suggested-by:
Richard Weinberger <richard@nod.at> Suggested-by:
Andras Szemzo <szemzo.andras@gmail.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com>
-
Cyrille Pitchen authored
The patch checks whether the Quad Enable bit is already set in the Status Register. If so, the function exits immediately with a successful return code. Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com> Reviewed-by:
Jagan Teki <jagan@openedev.com> Acked-by:
Marek Vasut <marek.vasut@gmail.com>
-
Ricardo Ribalda authored
Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep their configuration data and (optionally) some user data. The protocol of this flash follows most of the spi-nor standard. With the following differences: - Page size might not be a power of two. - The address calculation (default addressing mode). - The spi nor commands used. Protocol is described on Xilinx User Guide UG333 Signed-off-by:
Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Reviewed-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Cyrille Pitchen <cyrille.pitchen@atmel.com>
-
Sascha Hauer authored
The user visible change here is that mtd partitions get an of_node link in sysfs. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Rafał Miłecki authored
Some devices may have an extra TRX partition used as failsafe one. If we detect such partition we should set a proper name for it and don't parse it. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Acked-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Rafał Miłecki authored
This change simplifies main parsing loop logic a bit. In future it may be useful for moving TRX support to separated module / parser (if we implement support for them at some point). Finally parsing TRX at the end puts us in a better position as we have better flash layout knowledge. It may be useful e.g. if it appears there is more than 1 TRX partition. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Acked-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
- 08 Feb, 2017 13 commits
-
-
Rafał Miłecki authored
For reading flash content we use MMIO but it's possible to read only first 16 MiB this way. It's simply an arch design/limitation. To support flash sizes bigger than 16 MiB implement indirect access using ChipCommon registers. This has been tested using MX25L25635F. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Acked-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Brian Norris authored
From Boris: """ This pull request contains minor fixes/improvements on existing drivers: - sunxi: avoid busy-waiting for NAND events - ifc: fix ECC handling on IFC v1.0 - OX820: add explicit dependency on ARCH_OXNAS in Kconfig - core: add a new manufacture ID and fix a kernel-doc warning - fsmc: kill pdata support - lpc32xx_slc: remove unneeded NULL check """ Conflicts: include/linux/mtd/nand.h [Brian: trivial conflict in the comment section]
-
Nobuhiro Iwamatsu authored
Trivial typo fix in comment. Signed-off-by:
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Zach Brown authored
ONFI compliant chips contain the values for the max_bb_per_die and blocks_per_die fields in the parameter page. When the ONFI paged is retrieved/parsed the chip's fields are set by the corresponding fields in the param page. Signed-off-by:
Zach Brown <zach.brown@ni.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electron.com> Acked-by:
Brian Norris <computersforpeace@gmail.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Zach Brown authored
Implement the new mtd function 'max_bad_blocks'. Using the chip's max_bb_per_die and blocks_per_die fields to determine the maximum bad blocks to reserve for an MTD. Signed-off-by:
Jeff Westfahl <jeff.westfahl@ni.com> Signed-off-by:
Zach Brown <zach.brown@ni.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electron.com> Acked-by:
Brian Norris <computersforpeace@gmail.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Zach Brown authored
The fields max_bb_per_die and blocks_per_die are useful determining the number of bad blocks a MTD needs to allocate. How they are set will depend on if the chip is ONFI, JEDEC or a full-id entry in the nand_ids table. Signed-off-by:
Zach Brown <zach.brown@ni.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electron.com> Acked-by:
Brian Norris <computersforpeace@gmail.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Arnd Bergmann authored
pci_read_config_word() might fail and not initialize its output, as pointed out by older versions of gcc when using the -Wmaybe-unintialized flag: drivers/mtd/maps/ichxrom.c: In function ‘ichxrom_cleanup’: drivers/mtd/maps/ichxrom.c:63:2: error: ‘word’ is used uninitialized in this function [-Werror=uninitialized] This is apparently a correct warning, though it does not show up with newer compilers. Changing the code to not attempt to write back uninitialized data into PCI config space is a correct fix for the problem and avoids the warning. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Marek Vasut <marex@denx.de> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Jeff Westfahl authored
If implemented, 'max_bad_blocks' returns the maximum number of bad blocks to reserve for a MTD. An implementation for NAND is coming soon. Signed-off-by:
Jeff Westfahl <jeff.westfahl@ni.com> Signed-off-by:
Zach Brown <zach.brown@ni.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electron.com> Acked-by:
Brian Norris <computersforpeace@gmail.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Masahiro Yamada authored
- "This functions return ..." -> "This function returns ..." - "I you want ..." -> "If you want ..." Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Arnd Bergmann authored
kernelci.org reports a warning for this driver, as it copies a local variable into a 'const char *' string: drivers/mtd/maps/pmcmsp-flash.c:149:30: warning: passing argument 1 of 'strncpy' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] Using kstrndup() simplifies the code and avoids the warning. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Linus Walleij authored
In order to support device tree probing of Gemini NOR flash chips, a certain register in the syscon needs to be poked to enable parallel flash mode. Such things used to happen in "necessarily different" board file code, and this indeed was also done for the Gemini, so the MTD driver could treat it as any memory-mapped NOR flash, but this is not the way in the future: board files need to go, and hardware concerns distributed down to the applicable drivers. This adds a hook in the same way that the Versatile did: if the Kconfig symbol is not selected the net total of supporting Gemini should be zero bytes of added code. To live up to this promise, also the return value error print from the Versatile extra probe call get to be removed in this patch, all printing need to happen in the add-ons. Cc: Janos Laube <janos.dev@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
John Crispin authored
This patch updates my email address as I no longer have access to the old one. Signed-off-by:
John Crispin <john@phrozen.org> Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-
Linus Walleij authored
This adds device tree bindings for the Cortina systems Gemini flash controller, a simple physmap which however need a few syscon bits to be poked to operate properly. Cc: Janos Laube <janos.dev@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: devicetree@vger.kernel.org Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Reviewed-by:
Marek Vasut <marek.vasut@gmail.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
-