- 05 Oct, 2010 2 commits
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Ben Skeggs authored
Nouveau will need this on GeForce 8 and up to account for the GPU reordering physical VRAM for some memory types. Reviewed-by:
Jerome Glisse <jglisse@redhat.com> Acked-by:
Thomas Hellström <thellstrom@vmware.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Existing core code/drivers call drm_mm_put_block on ttm_mem_reg.mm_node directly. Future patches will modify TTM behaviour in such a way that ttm_mem_reg.mm_node doesn't necessarily belong to drm_mm. Reviewed-by:
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- 04 Oct, 2010 20 commits
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Roy Spliet authored
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Ben Skeggs authored
This was disabled previously because of some uncertainty that +2 was indeed the voltage. It appears it is, checked on a NVA8 and a NVA3M. Signed-off-by: -
Emil Velikov authored
This fixes issues bug 30370 and prevents another possible divide by zero on the original nv50 cards, by returning -ENOENT Signed-off-by:
Emil Velikov <eeydev@nottingham.ac.uk> Signed-off-by:
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Francisco Jerez authored
Reported-by:
Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by:
Francisco Jerez <currojerez@riseup.net> Tested-by:
Maarten Maathuis <madman2003@gmail.com> Tested-by:
Xavier Chantry <chantry.xavier@gmail.com> Tested-by:
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Francisco Jerez authored
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Francisco Jerez authored
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Francisco Jerez authored
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Francisco Jerez authored
Mainly to make room for inter-channel sync. Signed-off-by:
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Marcin Kościelnicki authored
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Ben Skeggs authored
Should fix a DMA race condition I've never seen myself, but could be the culprit in some random hangs that have been reported. Signed-off-by: -
Francisco Jerez authored
It's an unrelated PLL filtering control bit, leave it alone when changing the CRTC-encoder binding. Signed-off-by:
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Francisco Jerez authored
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Francisco Jerez authored
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Ben Skeggs authored
This should fix eDP on certain laptops with 18-bit panels, we were rejecting the panel's native mode due to thinking there was insufficient bandwidth for it. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
This will end up quite different, it makes sense for it to be completely separate. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
On certain boards, there's BIOS scripts and memory timings that need to be modified with the memclk. Just pass in the entire perflvl struct and let the chipset-specific code decide what to do. Signed-off-by: -
Ben Skeggs authored
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Adam Jackson <ajax@redhat.com> Signed-off-by:
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Roy Spliet authored
This isn't correct everywhere yet, but since we don't use the data yet it's perfectly safe to push in, and the information we gain from logs will help to fix the remaining issues. v2 (Ben Skeggs <bskeggs@redhat.com>): - fixed up formatting - free parsed timing info on takedown - switched timing table printout to debug loglevel Signed-off-by:
Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by:
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- 24 Sep, 2010 18 commits
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Ben Skeggs authored
Just in case someone, somewhere, does something difficult. This also removes one path that was different between fermi and non-fermi. Signed-off-by: -
Ben Skeggs authored
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Francisco Jerez authored
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Francisco Jerez authored
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Francisco Jerez authored
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Francisco Jerez authored
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Francisco Jerez authored
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Francisco Jerez authored
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Francesco Marella authored
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Francesco Marella <fmarl@paranoici.org> Signed-off-by:
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Francisco Jerez authored
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Francisco Jerez authored
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Ben Skeggs authored
nouveau_bios_fp_mode() zeroes the mode struct before filling in relevant entries. This nukes the mode id initialised by drm_mode_create(), and causes warnings from idr when we try to remove the mode. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
Somehow fixes some corruption seen in KDE.. Signed-off-by: -
Ben Skeggs authored
Very useful for debugging buffer migration issues. Signed-off-by: -
Martin Peres authored
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Martin Peres <martin.peres@ensi-bourges.fr> Signed-off-by:
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Ben Skeggs authored
Fixes DP output on a GTX 465 board I have. Signed-off-by: -
Francisco Jerez authored
Used on nv17-nv28, they contain memory clocks and timings, only one of the table entries can actually be used, depending on the RAMCFG straps, and it's usually higher than the frequency programmed on boot by the BIOS. The memory timings listed in table version 0x1x are used to init the 0x12xx range but they aren't required for reclocking to work. Signed-off-by:
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